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Datei
TEM_uni_5_adc_stream.vhd
=> AD7356_12_SDO_A, AD7356_SDO_B => AD7356_12_SDO_B); AD7356_34: AD7356 port map( clk80 => clk80, data_ready => AD7356_34_data_ready, data_a => AD7356_3_data, data_b => AD7356_4_data, AD7356_nCS => AD7356_34_nCS, AD7356_SCK => AD7356_34_SCK, AD7356_SDO_A => AD7356_34_SDO_A, AD7356_SDO_B => AD7356_34_SDO_B); AD7356_56: AD7356 port map( clk80 => clk80, data_ready => AD7356_56_data_ready, data_a => AD7356_5_data, data_b
in „Wie Clockdomain crossing für FT232H, wie debuggen?“ · FPGA, VHDL & Co. ·
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Datei
TEM_uni_5_adc_stream.vhd
=> AD7356_12_SDO_A, AD7356_SDO_B => AD7356_12_SDO_B); AD7356_34: AD7356 port map( clk80 => clk80, data_ready => AD7356_34_data_ready, data_a => AD7356_3_data, data_b => AD7356_4_data, AD7356_nCS => AD7356_34_nCS, AD7356_SCK => AD7356_34_SCK, AD7356_SDO_A => AD7356_34_SDO_A, AD7356_SDO_B => AD7356_34_SDO_B); AD7356_56: AD7356 port map( clk80 => clk80, data_ready => AD7356_56_data_ready, data_a => AD7356_5_data, data_b
in „Wie Clockdomain crossing für FT232H, wie debuggen?“ · FPGA, VHDL & Co. ·
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Datei
TEM_uni_5_adc_stream_bench.vhd
LED_o: out std_logic; -- FT232RL UART FT232RL_RX: in std_logic; FT232RL_TX: out std_logic; -- ADCs AD7356_12_nCS: out std_logic; AD7356_12_SCK: out std_logic; AD7356_12_SDO_A: in std_logic; AD7356_12_SDO_B: in std_logic; AD7356_34_nCS: out std_logic; AD7356_34_SCK: out std_logic; AD7356_34_SDO_A: in std_logic
in „Wie Clockdomain crossing für FT232H, wie debuggen?“ · FPGA, VHDL & Co. ·
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Datei
AD7356.vhd
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.ALL; entity AD7356 is Port( clk80 : in std_logic; data_ready : out std_logic; data_a : out std_logic_vector(11 downto 0); data_b : out std_logic_vector(11 downto 0); AD7356_nCS : out std_logic; AD7356_SCK : out std_logic; AD7356_SDO_A : in std_logic; AD7356_SDO_B : in std_logic); end AD7356; architecture Behavioral of AD7356 is signal counter :unsigned(3 downto 0):=(others => '0'); signal data_buffer_a, data_buffer_b : std_logic_vector
in „Wie Clockdomain crossing für FT232H, wie debuggen?“ · FPGA, VHDL & Co. ·
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Datei
ADUM_AD7356.vhd
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.ALL; entity ADUM_AD7356 is Port( clk80 : in std_logic; data_ready : out std_logic; data_a : out std_logic_vector(11 downto 0); data_b : out std_logic_vector(11 downto 0); AD7356_nCS : out std_logic; AD7356_SCK : out std_logic; AD7356_SDO_A : in std_logic; AD7356_SDO_B : in std_logic); end ADUM_AD7356; architecture Behavioral of ADUM_AD7356 is signal counter :unsigned(3 downto 0):=(others => '0'); signal data_buffer_a, data_buffer_b
in „Wie Clockdomain crossing für FT232H, wie debuggen?“ · FPGA, VHDL & Co. ·
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PDF
Rauschen.pdf
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 AD7356_B |12 Bit |5 MSamples/s |64k Samples (Es wurden nur 11 Bits verwendet - 6,54 mV/Kanal) 45000 41057 40000 35000 30000 24464 25000 20000 15000 10000 5000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 14 0 0 0
in „Noch ein ADC Board für Trenz Electronic FPGA Modul“ · Projekte & Code ·