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4 Treffer für "AD7401" Suchergebnisse für ""AD7401""

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  • Datei

    toplevel.vhd

    Sinc_filt generic map ( DECIMATOR_M_BIT_SIZE => 5 ) -- M = 2^DECIMATOR_M_BIT_SIZE Port map( Mclk => AD7401A_ADC_Mclk_s, Mdata => AD7401A_ADC_Mdat_i, rst => rst_s, DataRate_clk => DataRate_clk_s, done => isSinc_filt_done_s, DataOut => sinc_filt_dout_s); -- Mclk nach draßen AD7401A_ADC_nMclk_s <= not AD7401A_ADC_Mclk_s; AD7401A_ADC_Mclk_inst : ODDR2 Port map(Q => AD7401A_ADC_Mclk_o, C0 => AD7401A_ADC_Mclk_s, C1 => AD7401A_ADC_nMclk_s, CE => '1', D0 => '1', D1 => '0', R => '0', S => '0'); --AD7401A_ADC_Mclk_o <= AD7401A_ADC_Mclk_s

    in „Frage zum Theta Delta-Sigma AD“ · FPGA, VHDL & Co. ·

  • PDF

    AD7401.pdf

    Isolated Sigma-Delta Modulator AD7401 FEATURES GENERAL DESCRIPTION 1 20 MHz maximum external clock rate The AD7401 is a second-order, sigma-delta (Σ-Δ) modulator Second-order modulator that converts an analog input signal into a high speed

    in „Verilog nach VHDL umsetzen“ · FPGA, VHDL & Co. ·

  • Datei

    toplevel_TB.vhd

    CLK_50MHZ, SW => SW, LED => LED, RS232_DCE_RXD => RS232_DCE_RXD, RS232_DCE_TXD => RS232_DCE_TXD, AD7401A_ADC_Mclk_o => AD7401A_ADC_Mclk_o, AD7401A_ADC_Mdat_i => AD7401A_ADC_Mdat_i, LTC2624_DAC_nCS_o => LTC2624_DAC_nCS_o, LTC2624_DAC_SCK_o => LTC2624_DAC_SCK_o, LTC2624_DAC_SDI_o => LTC2624_DAC_SDI_o,

    in „Frage zum Theta Delta-Sigma AD“ · FPGA, VHDL & Co. ·

  • PDF

    TMC4671-LA_datasheet.pdf

    external delta sigma modulators is intended for external isolated sigma delta modulators, such as AD7401 (with MCLK input driven by TMC4671), or AD7402 (with MCLK output to drive TMC4671). In addition, the external delta sigma interface supports the use of simple comparator with a R-C-R network as external

    in „Schaltplan/Layout Kontrolle BLDC Regler“ · Platinen ·