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Datei
AD7961_TB.vhd
library ieee; use ieee.std_logic_1164.all; entity tb_AD7960_conversion_freq is end tb_AD7960_conversion_freq; architecture tb of tb_AD7960_conversion_freq is component AD7960_conversion_freq port (DINp : in std_logic; DCOp : out std_logic; DCIp : in std_logic
in „ADC IP für AD7961 funktioniert nach synthese nicht“ · FPGA, VHDL & Co. ·
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Datei
tb_AD7960.vhd
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library work; entity tb_AD7960 is end tb_AD7960; architecture tb of tb_AD7960 is -- inside FPGA signal clk250 : std_logic := '0'; signal data_ready : std_logic := '0'; signal data : std_logic_vector(17 downto 0) := (others => '0
in „ADC IP für AD7961 funktioniert nach synthese nicht“ · FPGA, VHDL & Co. ·
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Datei
tb_FIR_AD7960.vhd
testbench -- -- This testbench instantiates your generated FIR Compiler core -- instance named "FIR_AD7960". -- -- Use Vivado's Run Simulation flow to run this testbench. See the Vivado -- documentation for details. -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity tb_FIR_AD7960 is end tb_FIR_AD7960; architecture tb of tb_FIR_AD7960 is ----------------------------------------------------------------------- -- Timing constants -----------------------------------------------
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Datei
AD7960_sim.vhd
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use ieee.math_real.all; entity AD7960_sim is port ( CLKp : in std_logic; CLKn : in std_logic; CNVp : in std_logic; CNVn : in std_logic; DCOp : out std_logic; DCOn : out std_logic; Dp : out std_logic; Dn : out std_logic; EN : in std_logic_vector(3 downto 0) ); end AD7960_sim; architecture sim of AD7960_sim is --- CLOCK --- signal counter500 : integer range 0 to 99 := 0; signal CLKp_buff : std_logic := '0'; signal CNVp_buff : std_logic := '0'; --- DATA --- type ROM512kx18
in „ADC IP für AD7961 funktioniert nach synthese nicht“ · FPGA, VHDL & Co. ·
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Datei
AD7960.vhd
IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library UNISIM; use UNISIM.Vcomponents.all; entity AD7960 is port ( CLK250 : in std_logic; data_ready : out std_logic; data : out std_logic_vector(17 downto 0); EN : out std_logic_vector(3 downto 0); CLKp : out std_logic; CLKn : out std_logic; CNVp : out
in „ADC IP für AD7961 funktioniert nach synthese nicht“ · FPGA, VHDL & Co. ·
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Datei
AD7961.vhd
IEEE.NUMERIC_STD.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; entity AD7960_conversion_freq is Generic ( num_bits : positive := 16; clk_freq : positive := 100; -- MHz sync_clk_freq : positive := 220; --MHz tMSB : positive := 300; -- ns tCNVH : positive := 130 -- ns ); Port
in „ADC IP für AD7961 funktioniert nach synthese nicht“ · FPGA, VHDL & Co. ·