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LTC1407CMSE.pdf
LTC1407/LTC1407A Serial 12-Bit/14-Bit, 3Msps Simultaneous Sampling ADCs with Shutdown U FEATURES DESCRIPTIO ® 3Msps Sampling ADC with Two Simultaneous TheLTC 1407/LTC1407Aare12-bit/14-bit,3MspsADCs Differential
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1407fa.pdf
LTC1407/LTC1407A Serial 12-Bit/14-Bit, 3Msps Simultaneous Sampling ADCs with Shutdown U FEATURES DESCRIPTIO ® ■ 3Msps Sampling ADC with Two Simultaneous TheLTC 1407/LTC1407Aare12-bit/14-bit,3MspsADCs Differential
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LTC1407.vhd
- Engineer: Lothar Miller -- -- Create Date: 22:50:57 07/26/2009 -- Design Name: -- Module Name: LTC1407 - Behavioral ---------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity LTC1407 is Port ( clk50 : in STD_LOGIC; cs : in
in „Der vhdl-Schnipsel-Anfängerfragen Thread“ · FPGA, VHDL & Co. ·
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LTC1407_tb.vhdl
TestData IS ARRAY (NATURAL range <>) OF StepData; CONSTANT MyAdrSize : INTEGER := 20; COMPONENT LTC1407 Port ( clk50 : in STD_LOGIC; cs : in STD_LOGIC; -- chip-select: ADC starts with setting cs high frc : in STD_LOGIC; -- free running conversion (high) or single shot (low) sck : out STD_LOGIC; conv
in „Seltsame (Neben-)Effekte in der Simulation“ · FPGA, VHDL & Co. ·
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Datei
sr_adc4.vhdl
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- Module to communicate with LTC1407 -- can be used for single-shot conversion (both channels) or -- free running conversion. -- At free running conversion, memory address lines will be incremented on each sample Entity sr_adc4 is Generic
in „Der vhdl-Schnipsel-Anfängerfragen Thread“ · FPGA, VHDL & Co. ·
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Datei
sr_adc.vhdl
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- Module to communicate with LTC1407 -- can be used for single-shot conversion (both channels) or -- free running conversion. -- At free running conversion, memory address lines will be incremented on each sample entity sr_adc is Port
in „Der vhdl-Schnipsel-Anfängerfragen Thread“ · FPGA, VHDL & Co. ·
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Datei
sr_adc.vhdl
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- Module to communicate with LTC1407 -- can be used for single-shot conversion (both channels) or -- free running conversion. -- At free running conversion, memory address lines will be incremented on each sample entity sr_adc is Port
in „Der vhdl-Schnipsel-Anfängerfragen Thread“ · FPGA, VHDL & Co. ·
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Datei
sr_adc5.vhdl
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- Module to communicate with LTC1407 -- can be used for single-shot conversion (both channels) or -- free running conversion. -- At free running conversion, memory address lines will be incremented on each sample entity sr_adc5 is Port
in „Der vhdl-Schnipsel-Anfängerfragen Thread“ · FPGA, VHDL & Co. ·
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FPGA_Kits_Vergleich_120205.pdf
shared with PMOD) AC-97 Audio Codex - - Line in/out, mic, headphone, - - - LM4550 ADC 2 x 14bit LTC1407A - - - with pre-amp LTC6912 - - 1.5Ms/s DAC - - - 4 x 12bit (LTC2624) - - Oscillator 100 / 66.7 / 40 MHz 100 MHz 100 MHz 50MHz and 66MHz 50MHz 100 / 50 / 25 MHz I/O 2x PMOD (12pin) =16 I/O 4x PMOD
in „Vergleich und Erfahrung zu LX9 MicroBoard, Nexys 3 und Atlys“ · FPGA, VHDL & Co. ·
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Engeler_DCF77.pdf
PGA BF245A A/D Random Phase Cor- Second Time LCD JFET delay detect relate detect decode LTC1562 LTC1407 8th order 14 bit bandpass 930 kS/s synck mulate Ssyncd Debug D/A LTC2624 HKW FTD02011R 4 channel antenna USB Oscillator Fig. 24. Block diagram of Demonstration Receiver implementing the Goertzel-PM
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Diplomarbeit_PID.pdf
-3E Starter Kit verfügt über einen 2-Kanal 14-Bit Analog-Digital-Wandler-Chip (Linear Technology LTC1407A-1). Diesem vorgeschaltet ist ein Verstärkerbaustein (Linear Technology LTC6912-1) der eine Spannungsverstärkung um die Faktoren 0, 1, 2, 5, 10, 20, 50 oder 100 vornehmen kann. Sowohl der AD-Wandler