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Datei
PCM_master.vhd
integer:= 16 ); port ( -- this device's ports CLK : in std_logic; -- main clock the same as SCK for PCM5142 BCK_OUT : out std_logic; LRCK_OUT : out std_logic; DIN_OUT : out std_logic; -- output data --> is PCM5142 audio input data! GND_OUT : out std_logic_vector(20 downto 0) ) ; end PCM_MASTER; architecture
in „DDS mit DE0-Nano Board nur niedrige Frequenzen?“ · FPGA, VHDL & Co. ·
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Datei
test_main.c
activate interrupts globally while(1) { avr_spi_master_init(); while(1) { // send 0b00000000 to pcm 5142 SPDR = 0x00; while(!(SPSR & (1<<SPIF))); // wait until transmission complete // send 0b00000000 to pcm 5142 so we are on page 0 SPDR = 0x00; while(!(SPSR & (1<<SPIF))); // wait until transmission
in „SPI mit Atmega8 zu PCM5142 klappt nicht!“ · Mikrocontroller und Digitale Elektronik ·
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Datei
avrspi.c
= ~(1<<PB4); // MISO as input! // PORTB &= ~(1<<PB2); // set SS to Vcc PORTB |= (1<<PB0); // set PCM5142 so SPI Mode SPCR |= (1<<MSTR); // set as master SPCR |= (1<<SPR0); // clock divided by 128 SPCR &= ~(1<<SPR1); SPCR &= ~(1<<CPOL); // clock polarity setting SPCR &= ~(1<<CPHA); // Clock phase sample
in „SPI mit Atmega8 zu PCM5142 klappt nicht!“ · Mikrocontroller und Digitale Elektronik ·
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Datei
spi.c
function is for initialization of the AVR's SPI-Module // it will set it to SPI-Master Mode // for PCM5142 clock phase "CPHA" hast to be set to "1" void avr_spi_master_init(void) { DDRB |= (1<<PB2) | (1<<PB3) | (1<<PB5) | (1<<PB1); // SS, MOSI, SCK as outputs! as well as MODE_SELECT (MODE1) //DDRB &= ~
in „AVR ATMEGA8 hex file erstellen“ · Mikrocontroller und Digitale Elektronik ·
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Datei
PCM_master_tb.vhd
device under test component PCM_MASTER port ( CLK : in std_logic; -- main clock the same as SCK for PCM5142 BCK_OUT : out std_logic; LRCK_OUT : out std_logic; DIN_OUT : out std_logic; -- output data --> is PCM5142 audio input data! GND_OUT : out std_logic_vector(20 downto 0)); end component; -- signals
in „DDS mit DE0-Nano Board nur niedrige Frequenzen?“ · FPGA, VHDL & Co. ·
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Datei
PCM_master.vhd
( -- this device's ports CLK : in std_logic; -- main clock the same as SCK for PCM5142 BCK_OUT : out std_logic; LRCK_OUT : out std_logic; DIN_OUT : out std_logic; -- output data --> is PCM5142 audio input data! --CLK_OUT : out std_logic; GND_OUT : out std_logic_vector(20 downto 0) )
in „DDS mit DE0-Nano Board nur niedrige Frequenzen?“ · FPGA, VHDL & Co. ·
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Datei
DDS_tb.vhd
my device under test component DDS port ( CLK : in std_logic; -- main clock the same as SCK for PCM5142 FREQ_INC : in std_logic_vector (7 downto 0); BCK : in std_logic; DIN_CNT : in integer; DOUT : out std_logic_vector (31 downto 0)); end component DDS; -- signals to be wired signal CLK_DUT : std_logic
in „DDS mit DE0-Nano Board nur niedrige Frequenzen?“ · FPGA, VHDL & Co. ·