library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use std.textio.all; use ieee.std_logic_textio.all; entity fileio is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; sinus : out STD_LOGIC_VECTOR (11 downto 0)); end fileio; -- http://www.xilinx.com/itp/xilinx8/books/data/docs/xst/xst0070_9.html architecture Behavioral of fileio is type sinmemory is array (0 to 7) of integer; signal sinetable: sinmemory; signal sinecounter: integer range 0 to 7; signal sin : STD_LOGIC_VECTOR (11 downto 0); signal str : string(1 to 100); begin
