1 | Started : "Fit".
|
2 | CS: block property: block_name=/HC573/EXPANDED_FlattenFull/HC573/my_latch<6>1 prop_name=TYPE prop_terse=XDM_PROPERTY_STRING "TYPE" "INV"
|
3 |
|
4 | CS: block property: block_name=/HC573/EXPANDED_FlattenFull/HC573 prop_name=TYPE prop_terse=XDM_PROPERTY_STRING "TYPE" "HC573"
|
5 |
|
6 |
|
7 | Process "Fit" failed
|
Irgenwie kann ich überhaupt nicht erkenne was das Problem sein soll,
Synthese geht ohne Probleme durch, Code:
1 | ----------------------------------------------------------------------------------
|
2 | -- Create Date: 12:53:59 12/15/2009
|
3 | -- Module Name: HC573 - Behavioral
|
4 | ----------------------------------------------------------------------------------
|
5 | library IEEE;
|
6 | use IEEE.STD_LOGIC_1164.ALL;
|
7 | use IEEE.STD_LOGIC_ARITH.ALL;
|
8 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
9 |
|
10 | entity HC573 is
|
11 | Port ( addr_in : in STD_LOGIC_VECTOR (6 downto 0);
|
12 | addr_out : out STD_LOGIC_VECTOR (6 downto 0);
|
13 | latch : in STD_LOGIC
|
14 | );
|
15 | end HC573;
|
16 |
|
17 | architecture Behavioral of HC573 is
|
18 | signal my_latch : std_logic_vector(6 downto 0);
|
19 | begin
|
20 | my_latch <= addr_in when latch = '1' else "1010101";
|
21 | addr_out <= my_latch;
|
22 | end Behavioral;
|
