ick komme nicht mehr weiter. mehr als 3 Wochen suche ich den Fehler :(
Könnte an RCC-Einstellung sein?
mein RCC-Code ist folgendes:
Danke für Eure Hilfe!
/**
* @brief Configures the different system clocks.
*/
void RCC_Configuration(void)
{
/* RCC system reset(for debug purpose) */
RCC_DeInit();
/* Setup the microcontroller system. Initialize the Embedded Flash
Interface,
initialize the PLL and update the SystemFrequency variable. */
SystemInit();
/* Enable HSE */
RCC_HSEConfig(RCC_HSE_ON);
/* Wait till HSE is ready */
HSEStartUpStatus = RCC_WaitForHSEStartUp();
if(HSEStartUpStatus == SUCCESS)
{
/* Enable Prefetch Buffer */
FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
/* Flash 2 wait state */
FLASH_SetLatency(FLASH_Latency_2);
/* HCLK = SYSCLK */
RCC_HCLKConfig(RCC_SYSCLK_Div1);
/* PCLK2 = HCLK */
RCC_PCLK2Config(RCC_HCLK_Div1);
/* PCLK1 = HCLK/2 */
RCC_PCLK1Config(RCC_HCLK_Div2);
/* ADCCLK = PCLK2/4 */
RCC_ADCCLKConfig(RCC_PCLK2_Div4);
#ifndef STM32F10X_CL
/* PLLCLK = 8MHz * 7 = 56 MHz */
RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_7);
#else
/* Configure PLLs *********/
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
RCC_PREDIV2Config(RCC_PREDIV2_Div5);
RCC_PLL2Config(RCC_PLL2Mul_8);
/* Enable PLL2 */
RCC_PLL2Cmd(ENABLE);
/* Wait till PLL2 is ready */
while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
{}
/* PLL configuration: PLLCLK = (PLL2 / 5) * 7 = 56 MHz */
RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5);
RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_7);
#endif
/* Enable PLL */
RCC_PLLCmd(ENABLE);
/* Wait till PLL is ready */
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
{
}
/* Select PLL as system clock source */
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
/* Wait till PLL is used as system clock source */
while(RCC_GetSYSCLKSource() != 0x08)
{
}
}
/* Enable peripheral clocks -----------------*/
/* Enable DMA1 and DMA2 clocks */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1 | RCC_AHBPeriph_DMA2,
ENABLE);
/* Enable ADC1 and GPIOC clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC3 | RCC_APB2Periph_GPIOC |
RCC_APB2Periph_GPIOD, ENABLE);
/* Enable DMA1 or/and DMA2 clock */
RCC_AHBPeriphClockCmd(SPI_MASTER_DMA_CLK | SPI_SLAVE_DMA_CLK, ENABLE);
/* Enable CRC clock */ //für CRC_CalcBlockCRC
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE);
/* Resets the CRC Data register */ //für CRC_CalcBlockCRC
CRC_ResetDR();
/* KHM__SPI --------------------------*/
#ifdef USE_STM3210C_EVAL
/* Enable GPIO clock for SPI_MASTER and SPI_SLAVE */
RCC_APB2PeriphClockCmd(SPI_MASTER_GPIO_CLK | SPI_SLAVE_GPIO_CLK |
RCC_APB2Periph_AFIO, ENABLE);
/* Enable SPI_MASTER Periph clock */
RCC_APB1PeriphClockCmd(SPI_MASTER_CLK, ENABLE);
#else
/* Enable SPI_MASTER clock and GPIO clock for SPI_MASTER and SPI_SLAVE
*/
RCC_APB2PeriphClockCmd(SPI_MASTER_GPIO_CLK | SPI_SLAVE_GPIO_CLK |
SPI_MASTER_CLK, ENABLE);
#endif
/* Enable SPI_SLAVE Periph clock */
RCC_APB1PeriphClockCmd(SPI_SLAVE_CLK, ENABLE);
}
ADC.jpg
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