Timer 1 PWM Frequenz berechnen

/*            Bit 0,      CEN:            Counter enable:                 0 = Counter disabled / 1 = Counter enabled                                                                                                                                                                */

/*            Bit 1,      UDIS:           Update disable:                 The Update (UEV) event enabled                                                                                                                                                                            */

/*            Bit 2,      URS:            Update request source:          These events can be: Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller                                                                                */

/*            Bit 3,      OPM:            One pulse mode:                 Counter is not stopped at update event                                                                                                                                                                    */

/*            Bit 4,      DIR:            Direction:                      -                                                                                                                                                                                                         */

/*            Bits 6:5,   CMS[1:0]:       Center-aligned mode selection:  Center-aligned mode 3. The counter counts up and down alternatively                                                                                                                                       */

/*            Bit 7,      ARPE:           Auto-reload preload enable:     TIMx_ARR register is not buffered                                                                                                                                                                         */

/*            Bits 9:8,   CKD[1:0]:       Clock division:                 tDTS=tCK_INT                                                                                                                                                                                              */

/*            Bits 15:10, Reserved:                                       always read as 0

/*    -> CCMR1:   COMPAREMODREG1 = 0x00000060;                                                                                                                                                                                                                                      */

/*                                                                                                                                                                                                                                                                                  */

/*            Bits 1:0,   CC1S:           Capture/Compare 1 selection:    CC1 channel is configured as output                                                                                                                                                                       */

/*            Bit 2,      OC1FE:          Output Compare 1 fast enable:   CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles                */

/*            Bit 3,      OC1PE:          Output Compare 1 preload enable:Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately                                                                                */

/*            Bits 6:4,   OC1M:           Output Compare 1 mode:          PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’)   */

/*            Bit 7,      OC1CE:          Output Compare 1 clear enable:  OC1Ref is not affected by the ETRF Input

#define     PRESCALE      0x00000003 

#define     AUTORELOAD    0x00000064

#define     CLOCKCONFIG             0x00000000 //001D8402                                                                                           /**/

#define     CLOCKCONTROLL           0x01000081 //01000081                                                                                           /**/

#define     CLOCKENABLES            0x00000A75 

#define     CONRTOLLREG1A           0x00000060                                                                                                                                                                                                                                    /**/

#define     CONTROLLREG1B           0x00000061                                                                                                                                                                                                                                    /**/

#define     CONTROLLREG2            0x00000000                                                                                                                                                                                                                                    /**/

#define     PRESCALE                5                                                                                                                                                                                                                                    /**/

#define     AUTORELOAD              67//258                                                                                                                                                                                                                                    /**/

#define     COMPAREMODREG1          0x00000060                                                                                                                                                                                                                                    /**/

#define     COMPAREMODREG2          0x00000000                                                                                                                                                                                                                                    /**/

#define     COMPAREENABLEREG        0x00000011                                                                                                                                                                                                                                    /**/

#define     SLAVEMODECONTROLLREG    0x00000000                                                                                                                                                                                                                                    /**/

#define     COMPAREREG1             0x00000020                                                                                                                                                                                                                                    /**/

#define     COMPAREREG2             0x00000000                                                                                                                                                                                                                                    /**/

#define     STATUSREG               0x00000000                                                                                                                                                                                                                                    /**/

#define     INTERRUPTENABLEREG      0x00000002                                                                                                                                                                                                                                    /**/

#define     EVENTGENERATREG         0x00000003                                                                                                                                                                                                                                    /**/

#define     BRAKDEATTIMEREG         0x0000CCFF

#define     CONFIGREGLOWA           0x88888888                                                                                            /**/

#define     CONFIGREGHIGHA          0x888888BB                                                                                            /**/

void main(void)                                            //

{

    // Clocks

    RCC     ->  APB2ENR     =   CLOCKENABLES;               // Enable GPIOA, GPIOC, GPIOD, GPIOE, ADC1, Alternate function and Timer 1 clock

    RCC     ->  CFGR        =   CLOCKCONFIG;                // Clockconfigurations

    RCC     ->  CR          =   CLOCKCONTROLL;              // 8MHz, PLL enable

//    while(RCC -> CR   == (1<<1))                            // waiting for Clock is stabile

//    {                                                       //

//        __nop();                                            //

//    }                                                       //

    // GPIOs

    GPIOA   ->  CRH         =   CONFIGREGHIGHA;             // Ports configuriere as Input/Output

    // Timer

    // Timer1

    TIM1  ->  CR1     =   CONRTOLLREG1A;                    // Auto-Reload Register are puffered; Center Aligned Mode 3, up- and down. An Event is activate by under- and overflow ausgelöst.

    TIM1  ->  CR2     =   CONTROLLREG2;                     // Reset Controllregister 2

    TIM1  ->  PSC     =   PRESCALE;                         // Prescaler

    TIM1  ->  ARR     =   AUTORELOAD;                       // Auto-Reload Register

    TIM1  ->  CCMR1   =   COMPAREMODREG1;                   // Compare Mode Register 1  Outputcompare Mode

    TIM1  ->  CCMR2   =   COMPAREMODREG2;                   // Compare Mode Register 2  Output Compare 1 Mode; Output Compare 2 Mode 

    TIM1  ->  CCER    =   COMPAREENABLEREG;                 // Compare Enable Register; Compare 1 Output Enable; Compare 2 Output Enable

    TIM1  ->  SMCR    =   SLAVEMODECONTROLLREG;             // Slave Mode Controll Register

    TIM1  ->  CCR1    =   COMPAREREG1;                      // Compare Register 1

    TIM1  ->  CCR2    =   COMPAREREG2;                      // Compare Register 2

    TIM1  ->  SR      =   STATUSREG;                        // Status Register: Interrupt Flagbits

    TIM1  ->  DIER    =   INTERRUPTENABLEREG;               // Interrupt Enable Register: Interrupt Compare 1 und Compare 2 enable

    TIM1  ->  EGR     =   EVENTGENERATREG;                  // Event Generator Register: Update generation; Compare 1 Generation / Compare 2 Generation 

    TIM1  ->  BDTR    =   BRAKDEATTIMEREG;                  // Lock off, break inputs disable

    TIM1  ->  CR1     =   CONTROLLREG1B;                    // Timer 1 starten