Hello,
Please I need your advices,
I am trying to define one sram Model just for simulation with VERILOG:
CYPRESS CY62167EV30 MoBL 16 MBit(1M x 16)32 Byte = 2^4 x 16 bits in
order to test the sram controller.
So I did this:
module ram(Address,Clk,CS,ME,WE,Dout);
input[3:0] Address;
input Clk;
input CS;
input ME;
input WE;
inout[15:0] Dout;
// ----------------------------------------------------------
reg[15:0] memory[15:0]; // Memory block 32Bytes = 16x 2 x 8 Bits = 2^4 x
16 Bits
reg[15:0] Data_Read;
assign Dout=Data_Read;
// Memory Write Block
integer i;
parameter init="";
initial
begin
if(init=="file")
$readmemb("init.dat", memory);
else begin
if(init=="address") begin
for(i=0;i<=15;i=i+1)
memory[i]=i;
end
else begin
if(init=="random") begin
for(i=0;i<=15;i=i+1)
memory[i]= $random;
end
else begin
if(init=="zero") begin
for(i=0;i<=15;i=i+1)
memory[i]=0;
end
else begin
if(init=="x") begin
for(i=0;i<=15;i=i+1)
memory[i]=1'bx;
end
else begin
$display("Error: Incorrect parameter init=%s",init);
$stop;
end
end
end
end
end
end
always@(posedge Clk) begin
if(CS==1) begin
if(WE==1) begin
Data_Read<=16'bz;
//Write in the memory
memory[Address]<=Dout;
end
else begin
if(ME==1)
//Read from the memory
Data_Read<=memory[Address];
end
end
else Data_Read<=16'bz;
end
endmodule
After simulation I realise that my memory has 16 bits word for that
there is one Adress for each 16 bits see the attached files
So what I am doing wrong in order to get one address for each 8 Bits?
and when i tried this reg[7:0] memory[31:0] it didn't match to my Data
bus ?
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Memory_Output.PNG
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