Hello,
I am trying to implement a burst transcation with SDRAM using Avalon MM
Interface.
The following Verilog code works fine for burstcount = 2:
1
module hw_det_3by3(
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clk,
3
reset,
4
avs_csr_addr,
5
avs_csr_write,
6
avs_csr_writedata,
7
avs_csr_read,
8
avs_csr_readdata,
9
avm_sdram_addr,
10
avm_sdram_burstcount,
11
avm_sdram_read,
12
avm_sdram_waitrequest,
13
avm_sdram_readdatavalid,
14
avm_sdram_readdata
15
16
);
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18
input wire clk;
19
input wire reset;
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21
input wire [2:0] avs_csr_addr;
22
input wire avs_csr_write;
23
input wire [31:0] avs_csr_writedata;
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input wire avs_csr_read;
25
output wire [31:0] avs_csr_readdata;
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output wire [31:0] avm_sdram_addr;
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output wire [2:0] avm_sdram_burstcount;
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output wire avm_sdram_read;
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input wire avm_sdram_waitrequest;
31
input wire avm_sdram_readdatavalid;
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input wire [31:0] avm_sdram_readdata;
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reg [31:0] read_addr;
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reg load_minors = 0;
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reg count = 0;
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reg status = 0;
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reg [31:0] minor10;
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reg [31:0] minor11;
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reg [31:0] minor12;
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reg [31:0] minor20;
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reg [31:0] minor21;
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reg [31:0] minor22;
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reg sdram_read;
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reg [31:0] csr_readdata;
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assign avm_sdram_addr = read_addr;
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assign avm_sdram_burstcount = 2;
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assign avm_sdram_read = sdram_read;
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assign avs_csr_readdata = csr_readdata;
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always @ (posedge clk)
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begin
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if (avs_csr_write == 1)
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begin
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if (avs_csr_addr == 1)
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begin
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load_minors <= 1;
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read_addr <= avs_csr_writedata;
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end
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end
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if (load_minors == 1)
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begin
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load_minors <= 0;
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end
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end
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always @ (posedge clk)
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begin
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if (load_minors == 1)
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begin
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sdram_read <= 1;
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end
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else
79
begin
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if (avm_sdram_waitrequest == 0)
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begin
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sdram_read <= 0;
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end
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end
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end
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always @ (posedge clk or posedge reset)
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begin
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if (reset == 1)
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begin
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count <= 0;
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status <= 0;
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end
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else if(avm_sdram_readdatavalid)
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begin
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case (count)
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0: begin
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minor10 <= avm_sdram_readdata;
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end
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1: begin
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minor11 <= avm_sdram_readdata;
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status <= 1;
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end
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endcase
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count <= count + 1;
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end
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end
108
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always @ (posedge clk)
110
begin
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if(avs_csr_read == 1)
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begin
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case (avs_csr_addr)
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0: csr_readdata <= status;
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1: csr_readdata <= read_addr;
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2: csr_readdata <= minor10;
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3: csr_readdata <= minor11;
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endcase
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end
120
end
121
122
endmodule
Software Interface in NIOS:
1
#include <stdio.h>
2
#include "system.h"
3
#include <io.h>
4
#include <stdlib.h> /* rand(), RAND_MAX */
5
6
int main()
7
{
8
9
float n = 1.25;
10
float m = 2.5;
11
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printf("%x, %x\n", &n, &m);
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IOWR(HW_DET_3BY3_0_BASE, 1, &n);
15
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while (IORD(HW_DET_3BY3_0_BASE, 0) == 0){
17
printf("%x\n", IORD(HW_DET_3BY3_0_BASE, 0));
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}
19
printf("%x\n", IORD(HW_DET_3BY3_0_BASE, 1));
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printf("%x\n", IORD(HW_DET_3BY3_0_BASE, 2));
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printf("%x\n", IORD(HW_DET_3BY3_0_BASE, 3));
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return 0;
24
}
However, when I make slight variations to implement the same
functionality for a burst of 3 words, then I get problems - 'status'
never changes to 1.
Does anyone have an idea why that is? I have been trying to solve this
for the past few hours now...
Also, is there are a possibility I can monitor my signals
(avm_sdram_writerequest, avm_sdram_readdatavalid etc.) during runtime?
Many thanks in advance.
Jimmy
Hello Jimmy
>Also, is there are a possibility I can monitor my signals
When I'm right then you using the Altera Quartus II Software. In this
case you can use the SignalTap to monitor the Interface inside the fpga
see here: http://www.altera.com/literature/hb/qts/qts_qii53009.pdf>However, when I make slight variations to implement the same>functionality for a burst of 3 words, then I get problems - 'status'>never changes to 1.
Some times ago, I had a similar task. Write values from the MM-Interface
in SRAM via Avalon. But Why would you change this signal? In my project
i Used an DMA-Core and I set the burstlength in this core.
Best Reagards
Andreas
