LPC2468, Ethernet MAC und Interrupts

#include "mac.h"

#include "lpc2468.h"

#include "ucos_ii.h"

#include "os_cpu.h"

#include "packet.h"

static void mac_init_rx_descriptors(void);

static void mac_init_tx_descriptors(void);

static void mac_phy_interrupt(void);

static void mac_interrupt(void);

static void mac_write_phy(INT16U reg, INT16U val);

static INT16U mac_read_phy(INT16U reg);

EMAC_DMA_RAM ALIGN static char rx_buffer[MAC_RX_FRAGMENTS][ETH_FRAG_SIZE];

EMAC_DMA_RAM ALIGN static char tx_buffer[MAC_TX_FRAGMENTS][ETH_FRAG_SIZE];

OS_EVENT *tx_pkt_cnt;

EMAC_DMA_RAM static rx_tx_descriptor rx_desc[MAC_RX_FRAGMENTS];

EMAC_DMA_RAM static tstRxStatusDescriptor rx_status_desc[MAC_RX_FRAGMENTS];

EMAC_DMA_RAM static rx_tx_descriptor tx_desc[MAC_TX_FRAGMENTS];

EMAC_DMA_RAM static INT32U tx_status_desc[MAC_TX_FRAGMENTS];

void mac_init(void)

{

  INT32U dwID;

  tx_pkt_cnt = OSSemCreate(1);

  AHBCFG2 |= (BIT_17 | BIT_12);

  PCONP |= BIT_30; /* power up the mac */

  PINSEL2 |= (BIT_00 | BIT_02 | BIT_08 | /* select the rmii pins */

    BIT_16 | BIT_18 | BIT_20 | BIT_28 | BIT_30);

  PINSEL3 |= (BIT_00 | BIT_02); /* select the mdio and clk pins */

  MAC1 =  (BIT_08 | BIT_09 | BIT_10 | BIT_11 | BIT_14 | BIT_15); /* reset mac */

  Command = (BIT_03 | BIT_04 | BIT_05); /* reset the mac */

  MAC1 = 0; /* deassert the soft resets */

  MAC2 = (BIT_04 | BIT_05); /* enable crc and padding */

  IPGR = IPGR_DEFAULT; /* set the back-to-back inter packet gap */

  CLRT = CLRT_DEFAULT; /* set the collision window and retransmission count */

  MAXF = MAX_FRAME; /* maximum frame length */

  MCFG = (BIT_02 | BIT_04 | BIT_15); /* divide host clk by 20 and reset mii */

  MCFG ^= BIT_15; /* deassert the reset from the mii hardware */

  MCMD = 0;

  Command = (BIT_09 | BIT_06); /* enable the rmii and pass runt frames */

  SUPP = BIT_08; /* enable 100MBit mode */

  mac_write_phy(PHY_BCR, BIT_15); /* reset the phy */

  while(mac_read_phy(PHY_BCR) & (BIT_15 | BIT_11)); /* wait until reset done */

  dwID = (mac_read_phy(PHY_ID1) << 16); /* get PHY manufacturer and revision */

  dwID |= (mac_read_phy(PHY_ID2) & 0xFFF0);

  if(dwID != KSZ8001_ID) /* check if this is a KSZ8001L PHY */

  {

    return; /* abort if it's not */

  }

  mac_write_phy(PHY_ICS, BIT_08 | BIT_10); /* enable link interrupt */

  mac_write_phy(PHY_CTL, BIT_14); /* enable the link and act LEDs */

  mac_write_phy(PHY_BCR, BIT_12 | BIT_09); /* enable & start autonegotiation*/

  PINSEL4 |= BIT_22; /* enable EINT1 interrupt */

  VICVectPriority15 = 0; /* set up the phy interrupt */

  VICVectAddr15 = (INT32U)mac_phy_interrupt;

  VICIntEnable |= BIT_15; /* enable the link up/down interrupt */

  SA0 = (MAC_ADDRESS1 << 8) | MAC_ADDRESS2; /* set up the station address */

  SA1 = (MAC_ADDRESS3 << 8) | MAC_ADDRESS4;

  SA2 = (MAC_ADDRESS5 << 8) | MAC_ADDRESS6;

  RxFilterCtrl = (BIT_02 | BIT_05); /* allow broadcast and perfect */

  mac_init_rx_descriptors(); /* initialize rx descriptor table */

  mac_init_tx_descriptors(); /* initialize tx descriptor table */

  VICVectPriority21 = 0; /* set up the mac interrupt */

  VICVectAddr21 = (INT32U)mac_interrupt;

  VICIntEnable |= BIT_21; /* enable the mac interrupt */

  IntClear = 0xFFFFFFFF;

  IntEnable = BIT_03 | BIT_07;

  return;

}

void mac_tx_enable(void)

{

  Command |= BIT_01;

}

void mac_tx_disable(void)

{

  Command &= ~BIT_01;

}

void mac_rx_enable(void)

{

  Command |= BIT_00;

  MAC1 |=BIT_00;

}

void mac_rx_disable(void)

{

  Command &= ~BIT_00;

  MAC1 &= ~BIT_00;

}

char* mac_new_packet(void)

{

  INT8U err;

  INT16U idx;

  OSSemPend(tx_pkt_cnt, 0, &err); /* wait until memory is available */

  idx = TxProduceIndex;

  return tx_desc[idx].packet;

}

void mac_send_packet(INT16U size)

{

  INT16U idx = TxProduceIndex;

  tx_desc[idx].control = (BIT_31 | BIT_30 | (size - 1));

  idx++;

  if(idx == MAC_TX_FRAGMENTS)

  {

    idx = 0;

  }

  TxProduceIndex = idx;

}

static void mac_init_rx_descriptors(void)

{

  INT16U idx;

  for(idx = 0; idx < MAC_RX_FRAGMENTS; idx++) /* loop for each element */

  {

    rx_desc[idx].packet = &rx_buffer[idx][0]; /* set the buffer pointer */

    rx_desc[idx].control = (BIT_31 | (ETH_FRAG_SIZE - 1)); /* enable rx int */

    rx_status_desc[idx].status = 0; /* zero-out the status and hash fields */

    rx_status_desc[idx].hash = 0;

  }

  RxDescriptor = (INT32U)rx_desc; /* rx descriptor base */

  RxStatus = (INT32U)rx_status_desc; /* status descriptor base */

  RxDescriptorNumber = MAC_RX_FRAGMENTS - 1; /* number of rx descriptors */

  RxConsumeIndex = 0; /* begin at the first rx descriptor */

}

static void mac_init_tx_descriptors(void)

{

  INT16U idx;

  for(idx = 0; idx < MAC_TX_FRAGMENTS; idx++)

  {

    tx_desc[idx].packet = &tx_buffer[idx][0];

    tx_desc[idx].control = 0;

  }

  TxDescriptor = (INT32U)tx_desc;

  TxStatus = (INT32U)tx_status_desc;

  TxDescriptorNumber = MAC_TX_FRAGMENTS - 1; /* number of tx descriptors */

  TxProduceIndex = 0; /* begin at the first tx descriptor */

} /* end mac_init_tx_descriptors */

/* the phy calls this via external interrupt 1 every time a cable is plugged in or out. */

static void mac_phy_interrupt(void)

{

  INT16U interrupt = mac_read_phy(PHY_ICS); /* get the interrupt source */

  if(interrupt & BIT_00)

  {

    INT16U mode = (mac_read_phy(PHY_100BTX) & (BIT_04 | BIT_03 | BIT_02));

    switch(mode)

    {

      case MODE_10M_HALF_DUPLEX:

      {

        MAC2 = (BIT_04 | BIT_05 | BIT_07); /* crc, padding, half duplex */

        SUPP = 0; /* 10MBit mode */

        Command &= ~BIT_10; /* issue half duplex command */

        IPGT = 0x12; /* default setting for 10 MBits, half duplex */

        break;

      }

      case MODE_10M_FULL_DUPLEX:

      {

        MAC2 = (BIT_00 | BIT_04 | BIT_05 | BIT_07); /* crc, padding, full duplex */

        SUPP = 0; /* 10MBit mode */

        Command |= BIT_10; /* issue full-duplex command */

        IPGT = 0x15; /* default setting for 10 MBits, full duplex */

        break;

     }

      case MODE_100M_HALF_DUPLEX:

      {

        MAC2 = (BIT_04 | BIT_05 | BIT_07); /* crc, padding, half duplex */

        SUPP = BIT_08; /* enable 100MBit mode */

        Command &= ~BIT_10; /* issue half-duplex command */

        IPGT = 0x12; /* default setting for 100 MBits, half duplex */

        break;

      }

      case MODE_100M_FULL_DUPLEX:

      {

        MAC2 = (BIT_00 | BIT_04 | BIT_05 | BIT_07); /* crc, padding, full duplex */

        SUPP = BIT_08; /* enable 100MBit mode */

        Command |= BIT_10; /* issue full-duplex command */

        IPGT = 0x15; /* default setting for 100 MBits, full duplex */

        break;

      }

    }

    mac_rx_enable(); /* enable the receiver */

    mac_tx_enable(); /* enable the transmitter */

  }

  else if(interrupt & BIT_02)

  {

    mac_rx_disable(); /* disable the receiver */

    mac_tx_disable(); /* disable the transmitter */

  }

  EXTINT |= BIT_01;

}

static void mac_interrupt(void)

{

  INT32U int_status = IntStatus; /* get the interrupt source */

  IntClear = int_status; /* acknowledge interrupt */

  int_status &= IntEnable; /* mask out unwanted irq's */

  if(int_status)

  {

    if(int_status & BIT_00) /* rx overrun */

    {

      Command |= BIT_05; /* rx reset */

    }

    if(int_status & BIT_01) /* rx error */

    {

    }

    if(int_status & BIT_02) /* rx finished */

    {

    }

    if(int_status & BIT_03) /* rx done */

    {

      /* HIER STÜRZT DER KRAM AB */

      /*INT16U idx = RxConsumeIndex;

      packet_add(rx_desc[idx].packet, (rx_status_desc[idx].status & 0x7FF));

      idx++;

      if(idx == MAC_RX_FRAGMENTS)

      {

        idx = 0;

      }

      RxConsumeIndex = idx;*/

    }

    if(int_status & BIT_04) /* tx underrun */

    {

      Command |= BIT_04; /* tx reset */

    }

    if(int_status & BIT_05) /* tx error */

    {

    }

    if(int_status & BIT_06) /* tx finished */

    {

    }

    if(int_status & BIT_07) /* tx done */

    {

      OSSemPost(tx_pkt_cnt); /* increase the number of available tx buffers */

    }

    if(int_status & BIT_12) /* software interrupt */

    {

    }

    if(int_status & BIT_13) /* wakeup */

    {

    }

  }

}

static void mac_write_phy(INT16U reg, INT16U val)

{

  MADR = (reg & 0x1F); /* the register address. only bits 0..5 are valid. */

  MWTD = val; /* write data */

  while(MIND & BIT_00); /* wait until write cycle is complete */

}

static INT16U mac_read_phy(INT16U reg)

{

  MADR = (reg & 0x1F); /* the register address. only bits 0..5 are valid. */

  MCMD = BIT_00; /* issue a read command */

  while(MIND & BIT_00); /* wait until read operation is complete */

  MCMD = 0;

  return MRDD;

}