Hi,
so kannst Du das Beispiel bei Freescale Downloaden.
************************************************************************
** APPS NOTE AN1274
** SCI EXAMPLE
**
** This program illustrates the basic operation of transmitting and
** receiving data packets using the SCI on the 68HC708XL36 with CGMA.
** Assembled with IASM08 Ver. 3.03
************************************************************************
BAUD EQU $00 ; Baud rate set to default value.
SCC1 EQU $13 ; SCI Control Register 1
LOOPS EQU 7 ; Bit 7: Loop Mode Select Bit
ENSCI EQU 6 ; Bit 6: Enable SCI Bit
TXINV EQU 5 ; Bit 5: Transmit Inversion Bit
M EQU 4 ; Bit 4: Mode (Character Length) Bit
WAKE EQU 3 ; Bit 3: Wake-up Condition Bit
ILTY EQU 2 ; Bit 2: Idle Line Type Bit
PEN EQU 1 ; Bit 1: Parity Enable Bit
PTY EQU 0 ; Bit 0: Parity bit
SCC2 EQU $14 ; SCI Control Register 2
SCTIE EQU 7 ; Bit 7: SCI transmit Interrupt Enable
Bit
TCIE EQU 6 ; Bit 6: Transmission Complete
Interrupt Enable
; Bit
SCRIE EQU 5 ; Bit 5: SCI Receive Interrupt Enable
Bit
ILIE EQU 4 ; Bit 4: Idle Line Interrupt Enable
Bit
TE EQU 3 ; Bit 3: Transmitter Enable Bit
RE EQU 2 ; Bit 2: Receiver Enable Bit
RWU EQU 1 ; Bit 1: Receiver Wake Up Bit
SBK EQU 0 ; Bit 0: Send Break Bit
SCC3 EQU $15 ; SCI Control Register 3
R8 EQU 7 ; Bit 7: Received Bit 8
T8 EQU 6 ; Transmitted Bit 8
DMARE EQU 5 ; Bit 5: DMA Receive Enable Bit
DMATE EQU 4 ; Bit 4: DMA Transfer Enable Bit
ORIE EQU 3 ; Bit 3: Receiver Overrun Interrupt
Enable Bit
NEIE EQU 2 ; Bit 2: Receiver Noise Error Interrupt
Enable
; Bit
FEIF EQU 1 ; Bit 1: Receiver Framing Error
Interrupt Enable
; Bit
PEIE EQU 0 ; Bit 0: Receiver Parity Error
Interrupt Enable
; Bit
SCS1 EQU $16 ; SCI Status Register 1
SCTE EQU 7 ; Bit 7: SCI Transmitter Empty Bit
TC EQU 6 ; Bit 6: Transmission Complete Bit
SCRF EQU 5 ; Bit 5: SCI Receiver Full Bit
IDLE EQU 4 ; Bit 4: Receiver Idle Bit
OR EQU 3 ; Bit 3: Receiver Overrun Bit
NF EQU 2 ; Bit 2: Receiver Noise Bit
FE EQU 1 ; Bit 1: Receiver Framing Error Bit
PE EQU 0 ; Bit 0P: Receiver Parity Error Bit
SCS2 EQU $17 ; SCI Status Register 2
BKF EQU 1 ; Bit 1: Break Flag Bit
RPF EQU 0 ; Bit 0: Reception in Process Flag Bit
SCDR EQU $18 ; SCI Data Register
SCBR EQU $19 ; SCI Baud Rate Register
----------------------------------------------------------------------
ORG $6E00 ; Beginning of EPROM space on
XL36
DATA fcb 'This is a test'
fcb 13
initscitx: lda #$01
sta $1f ; Disable COP
lda #BAUD
sta SCBR
bset ENSCI,SCC1 ; Enable SCI
bset TE,SCC2 ; Enable Transmit
lda SCS1 ; Clear SCI Transmitter Empty
Bit
ldx #$00 ; Index Counter
getbyte: lda DATA,x ; Get the packet from "DATA{
incx ; Increment counter to get next
data byte
brclr SCTE,SCS1,* ; Wait until transmitter is
ready
sta SCDR ; Store Data in SCI Data
Register
cmp #$0D ; Is this the end of the
packet?
bne getbyte ; If not, then get another byte
to send
brclr TC,SCS1,* ; Wait for transmitter to finish
bclr TE,SCC2 ; Stop the transmitter
lda #$00
sta SCDR ; Clear the SCI Data Register
initscirx: bset ENSCI,SCC1 ; Enable SCI
bset RE,SCC2 ; Set Receive Enable
ldx #$00 ; Setup the index counter
**** Check the received character ****
next: brclr SCRF,SCS1,* ;Wait here until a chr comes
lda SCDR ; Get the Data from the SCI
Data Register
sta $50,x ; Store the data in RAM
cmp DATA,x ; Error checking
bne bad ; Run "bad" routine if data is bad
back: incx ; Increment index register to
receive next
; byte
cmp #$0D ; Is the data received the
"END of
; Packet"?
bne next ; If not then get next byte of
the packet
bclr RE,SCC2 ; Turn off the receiver
jmp initscitx ; Go back to the beginning.
************************************************************************
** bad routine
**
** This subroutine turns on an LED if an error has occurred.
************************************************************************
bad: stx $90 ; Save index register for later use
ldx #$ff
stx $00 ; Port A Data Direction
Register-output
stx $04 ; Port A Data Register - HIGH
ldx $90 ; Restore Index Register
bra back ; Always go back to main
program
************************************************************************
** Reset Vectors
**
************************************************************************
org $fffe
fdb initscitx
end
Eckhard
