Warum ist der Ausgang immer auf 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pwm1 is
    Port (
Oszilator       :   in     bit; Plus_Taster      :   in     std_ulogic;
Minus_Taster             :        in            std_ulogic;
Channel_1      :  out    std_ulogic;
Channel_2      :  out    std_ulogic;
Red_Frequenz_LED  :  out    std_ulogic);
end pwm1;

architecture behavior of pwm1 is

  constant   PWM_Frequenz  :  integer  :=   660;
  constant  PWM_Phase_MAX  :  integer  :=  330;

  signal     count_Red_Frequenz  :  unsigned(0 to 24) := 
"0000000000000000000000000";
  signal   count  : integer  range 0 to PWM_Frequenz;
  signal  PWM_Phase  :   integer range 0 to PWM_Phase_MAX := 0;
  signal  Signal_Channel_1  :  std_ulogic;
  signal  Signal_Channel_2  :  std_ulogic;
  signal  Red_Frequenz    :  std_ulogic;


begin


process (Oszilator)
  begin
    if Oszilator='1' and Oszilator'event
    then
        count_Red_Frequenz <= count_Red_Frequenz + 1;
    end if;
    Red_Frequenz_LED <= count_Red_Frequenz(0);
  end process;



process (PWM_Phase)
  begin
    if count_Red_Frequenz(0) = '1' and Plus_Taster = '1'
    then
      if PWM_Phase < PWM_Phase_MAX
      then
      PWM_Phase <= PWM_Phase + 1;
      end if;
    end if;

    if count_Red_Frequenz(0) = '1' and Minus_Taster = '1'
    then
      if PWM_Phase > 0
      then
      PWM_Phase <= PWM_Phase - 1;
      end if;
    end if;
  end process;


process (count)
  begin
    if count < PWM_Frequenz
    then
      count <= count + 1;
    else
      count <= 1;
    end if;
  end process;

process (Signal_Channel_1)
  begin
    if count < (PWM_Frequenz/2)
    then
    Signal_Channel_1 <= '1';
    else
    Signal_Channel_1 <= '0';
    end if;
  end process;


channel_1 <= signal_channel_1;

end behavior;