1 | void ClocksInit(void){
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2 |
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3 | uint32_t tempDFLL48CalibrationCoarse; /* used to retrieve DFLL48 coarse calibration value from NVM */
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4 |
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5 | /* ----------------------------------------------------------------------------------------------
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6 | * 1) Set Flash wait states for 48 MHz (per Table 37-40 in data sheet)
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7 | */
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8 |
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9 | NVMCTRL->CTRLB.bit.RWS = 1; /* 1 wait state required @ 3.3V & 48MHz */
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10 |
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11 | /* ----------------------------------------------------------------------------------------------
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12 | * 2) Enable XOSC32K clock (External on-board 32.768kHz oscillator), will be used as DFLL48M reference.
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13 | */
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14 |
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15 | // Configure SYSCTRL->XOSC32K settings
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16 | SYSCTRL_XOSC32K_Type sysctrl_xosc32k = {
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17 | .bit.WRTLOCK = 0, /* XOSC32K configuration is not locked */
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18 | .bit.STARTUP = 0x2, /* 3 cycle start-up time */
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19 | .bit.ONDEMAND = 0, /* Osc. is always running when enabled */
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20 | .bit.RUNSTDBY = 0, /* Osc. is disabled in standby sleep mode */
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21 | .bit.AAMPEN = 0, /* Disable automatic amplitude control */
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22 | .bit.EN32K = 1, /* 32kHz output is disabled */
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23 | .bit.XTALEN = 1 /* Crystal connected to XIN32/XOUT32 */
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24 | };
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25 |
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26 | SYSCTRL_OSC32K_Type sysctrl_osc32k = {
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27 | .bit.WRTLOCK = 0, /* OSC32K configuration is not locked */
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28 | .bit.STARTUP = 0x2, /* 3 cycle start-up time */
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29 | .bit.ONDEMAND = 0, /* Osc. is always running when enabled */
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30 | .bit.RUNSTDBY = 0, /* Osc. is disabled in standby sleep mode */
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31 | .bit.EN32K = 1, /* 32kHz output is disabled */
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32 | };
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33 |
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34 | // Write these settings
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35 | // SYSCTRL->XOSC32K.reg = sysctrl_xosc32k.reg;
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36 | SYSCTRL->OSC32K.reg = sysctrl_osc32k.reg;
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37 | // Enable the Oscillator - Separate step per data sheet recommendation (sec 17.6.3)
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38 | SYSCTRL->OSC32K.bit.ENABLE = 1;
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39 | // SYSCTRL->XOSC32K.bit.ENABLE = 1;
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40 |
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41 | // Wait for XOSC32K to stabilize
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42 | while(!SYSCTRL->PCLKSR.bit.OSC32KRDY);
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43 |
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44 | /* ----------------------------------------------------------------------------------------------
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45 | * 3) Put XOSC32K as source of Generic Clock Generator 1
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46 | */
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47 |
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48 | // Set the Generic Clock Generator 1 output divider to 1
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49 | // Configure GCLK->GENDIV settings
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50 | GCLK_GENDIV_Type gclk1_gendiv = {
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51 | .bit.DIV = 1, /* Set output division factor = 1 */
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52 | // .bit.ID = GENERIC_CLOCK_GENERATOR_XOSC32K /* Apply division factor to Generator 1 */
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53 | .bit.ID = 0x04
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54 | };
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55 | // Write these settings
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56 | GCLK->GENDIV.reg = gclk1_gendiv.reg;
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57 |
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58 | // Configure Generic Clock Generator 1 with XOSC32K as source
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59 | GCLK_GENCTRL_Type gclk1_genctrl = {
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60 | .bit.RUNSTDBY = 0, /* Generic Clock Generator is stopped in stdby */
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61 | .bit.DIVSEL = 0, /* Use GENDIV.DIV value to divide the generator */
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62 | .bit.OE = 0, /* Disable generator output to GCLK_IO[1] */
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63 | .bit.OOV = 0, /* GCLK_IO[1] output value when generator is off */
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64 | .bit.IDC = 1, /* Generator duty cycle is 50/50 */
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65 | .bit.GENEN = 1, /* Enable the generator */
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66 | .bit.SRC = 0x05, /* Generator source: XOSC32K output */
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67 | // .bit.ID = GENERIC_CLOCK_GENERATOR_XOSC32K /* Generator ID: 1 */
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68 | .bit.ID = 0x04
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69 | };
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70 | // Write these settings
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71 | GCLK->GENCTRL.reg = gclk1_genctrl.reg;
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72 | // GENCTRL is Write-Synchronized...so wait for write to complete
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73 | while(GCLK->STATUS.bit.SYNCBUSY);
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74 |
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75 | /* ----------------------------------------------------------------------------------------------
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76 | * 4) Put Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference)
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77 | */
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78 |
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79 | GCLK_CLKCTRL_Type gclk_clkctrl = {
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80 | .bit.WRTLOCK = 0, /* Generic Clock is not locked from subsequent writes */
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81 | .bit.CLKEN = 1, /* Enable the Generic Clock */
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82 | // .bit.GEN = GENERIC_CLOCK_GENERATOR_XOSC32K, /* Generic Clock Generator 1 is the source */
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83 | .bit.GEN = 0x04, /* Generic Clock Generator 1 is the source */
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84 | .bit.ID = 0x00 /* Generic Clock Multiplexer 0 (DFLL48M Reference) */
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85 | };
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86 | // Write these settings
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87 | GCLK->CLKCTRL.reg = gclk_clkctrl.reg;
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88 |
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89 | /* ----------------------------------------------------------------------------------------------
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90 | * 5) Enable DFLL48M clock
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91 | */
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92 |
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93 | // DFLL Configuration in Closed Loop mode, cf product data sheet chapter
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94 | // 17.6.7.1 - Closed-Loop Operation
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95 |
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96 | // Enable the DFLL48M in open loop mode. Without this step, attempts to go into closed loop mode at 48 MHz will
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97 | // result in Processor Reset (you'll be at the in the Reset_Handler in startup_samd21.c).
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98 | // PCLKSR.DFLLRDY must be one before writing to the DFLL Control register
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99 | // Note that the DFLLRDY bit represents status of register synchronization - NOT clock stability
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100 | // (see Data Sheet 17.6.14 Synchronization for detail)
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101 | while(!SYSCTRL->PCLKSR.bit.DFLLRDY);
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102 | SYSCTRL->DFLLCTRL.reg = (uint16_t)(SYSCTRL_DFLLCTRL_ENABLE);
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103 | while(!SYSCTRL->PCLKSR.bit.DFLLRDY);
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104 |
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105 | // Set up the Multiplier, Coarse and Fine steps
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106 | SYSCTRL_DFLLMUL_Type sysctrl_dfllmul = {
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107 | .bit.CSTEP = 31, /* Coarse step - use half of the max value (63) */
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108 | .bit.FSTEP = 511, /* Fine step - use half of the max value (1023) */
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109 | .bit.MUL = 1465 /* Multiplier = MAIN_CLK_FREQ (48MHz) / EXT_32K_CLK_FREQ (32768 Hz) */
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110 | };
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111 | // Write these settings
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112 | SYSCTRL->DFLLMUL.reg = sysctrl_dfllmul.reg;
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113 | // Wait for synchronization
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114 | while(!SYSCTRL->PCLKSR.bit.DFLLRDY);
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115 |
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116 | // To reduce lock time, load factory calibrated values into DFLLVAL (cf. Data Sheet 17.6.7.1)
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117 | // Location of value is defined in Data Sheet Table 10-5. NVM Software Calibration Area Mapping
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118 |
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119 | // Get factory calibrated value for "DFLL48M COARSE CAL" from NVM Software Calibration Area
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120 | tempDFLL48CalibrationCoarse = *(uint32_t*)FUSES_DFLL48M_COARSE_CAL_ADDR;
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121 | tempDFLL48CalibrationCoarse &= FUSES_DFLL48M_COARSE_CAL_Msk;
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122 | tempDFLL48CalibrationCoarse = tempDFLL48CalibrationCoarse>>FUSES_DFLL48M_COARSE_CAL_Pos;
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123 | // Write the coarse calibration value
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124 | SYSCTRL->DFLLVAL.bit.COARSE = tempDFLL48CalibrationCoarse;
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125 | // Switch DFLL48M to Closed Loop mode and enable WAITLOCK
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126 | while(!SYSCTRL->PCLKSR.bit.DFLLRDY);
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127 | SYSCTRL->DFLLCTRL.reg |= (uint16_t) (SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_WAITLOCK);
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128 |
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129 | /* ----------------------------------------------------------------------------------------------
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130 | * 6) Switch Generic Clock Generator 0 to DFLL48M. CPU will run at 48MHz.
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131 | */
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132 |
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133 | // Now that DFLL48M is running, switch CLKGEN0 source to it to run the core at 48 MHz.
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134 | // Enable output of Generic Clock Generator 0 (GCLK_MAIN) to the GCLK_IO[0] GPIO Pin
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135 | GCLK_GENCTRL_Type gclk_genctrl0 = {
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136 | .bit.RUNSTDBY = 0, /* Generic Clock Generator is stopped in stdby */
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137 | .bit.DIVSEL = 0, /* Use GENDIV.DIV value to divide the generator */
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138 | .bit.OE = 1, /* Enable generator output to GCLK_IO[0] */
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139 | .bit.OOV = 0, /* GCLK_IO[0] output value when generator is off */
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140 | .bit.IDC = 1, /* Generator duty cycle is 50/50 */
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141 | .bit.GENEN = 1, /* Enable the generator */
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142 | .bit.SRC = 0x07, /* Generator source: DFLL48M output */
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143 | .bit.ID = GENERIC_CLOCK_GENERATOR_MAIN /* Generator ID: 0 */
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144 | };
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145 | GCLK->GENCTRL.reg = gclk_genctrl0.reg;
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146 | // GENCTRL is Write-Synchronized...so wait for write to complete
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147 | while(GCLK->STATUS.bit.SYNCBUSY);
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148 |
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149 | // Direct the GCLK_IO[0] output to PA28
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150 | PORT_WRCONFIG_Type port0_wrconfig = {
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151 | .bit.HWSEL = 1, /* Pin# (28) - falls in the upper half of the 32-pin PORT group */
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152 | .bit.WRPINCFG = 1, /* Update PINCFGy registers for all pins selected */
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153 | .bit.WRPMUX = 1, /* Update PMUXn registers for all pins selected */
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154 | .bit.PMUX = 7, /* Peripheral Function H selected (GCLK_IO[0]) */
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155 | .bit.PMUXEN = 1, /* Enable peripheral Multiplexer */
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156 | .bit.PINMASK = (uint16_t)(1 << (28-16)) /* Select the pin(s) to be configured */
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157 | };
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158 | // Write these settings
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159 | PORT->Group[0].WRCONFIG.reg = port0_wrconfig.reg;
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160 |
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161 | /* ----------------------------------------------------------------------------------------------
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162 | * 7) Modify prescaler value of OSC8M to produce 8MHz output
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163 | */
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164 |
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165 | SYSCTRL->OSC8M.bit.PRESC = 0; /* Prescale by 1 */
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166 | SYSCTRL->OSC8M.bit.ONDEMAND = 0 ; /* Oscillator is always on if enabled */
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167 |
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168 | /* ----------------------------------------------------------------------------------------------
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169 | * 8) Put OSC8M as source for Generic Clock Generator 3
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170 | */
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171 |
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172 | // Set the Generic Clock Generator 3 output divider to 1
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173 | // Configure GCLK->GENDIV settings
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174 | GCLK_GENDIV_Type gclk3_gendiv = {
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175 | .bit.DIV = 1, /* Set output division factor = 1 */
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176 | .bit.ID = GENERIC_CLOCK_GENERATOR_OSC8M /* Apply division factor to Generator 3 */
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177 | };
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178 | // Write these settings
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179 | GCLK->GENDIV.reg = gclk3_gendiv.reg;
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180 |
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181 | // Configure Generic Clock Generator 3 with OSC8M as source
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182 | GCLK_GENCTRL_Type gclk3_genctrl = {
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183 | .bit.RUNSTDBY = 0, /* Generic Clock Generator is stopped in stdby */
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184 | .bit.DIVSEL = 0, /* Use GENDIV.DIV value to divide the generator */
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185 | .bit.OE = 0, /* Disable generator output to GCLK_IO[1] */
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186 | .bit.OOV = 0, /* GCLK_IO[2] output value when generator is off */
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187 | .bit.IDC = 1, /* Generator duty cycle is 50/50 */
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188 | .bit.GENEN = 1, /* Enable the generator */
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189 | .bit.SRC = 0x06, /* Generator source: OSC8M output */
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190 | .bit.ID = GENERIC_CLOCK_GENERATOR_OSC8M /* Generator ID: 3 */
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191 | };
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192 | // Write these settings
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193 | GCLK->GENCTRL.reg = gclk3_genctrl.reg;
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194 | // GENCTRL is Write-Synchronized...so wait for write to complete
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195 | while(GCLK->STATUS.bit.SYNCBUSY);
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196 |
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197 | /* ----------------------------------------------------------------------------------------------
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198 | * 9) Set CPU and APBx BUS Clocks to 48MHz
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199 | */
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200 | PM->CPUSEL.reg = PM_CPUSEL_CPUDIV_DIV1 ;
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201 | PM->APBASEL.reg = PM_APBASEL_APBADIV_DIV1_Val ;
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202 | PM->APBBSEL.reg = PM_APBBSEL_APBBDIV_DIV1_Val ;
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203 | PM->APBCSEL.reg = PM_APBCSEL_APBCDIV_DIV1_Val ;
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204 |
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205 | } // ClockSysInit48M()
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