1 | /**
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2 | * @brief Configures the System clock source, PLL Multiplier and Divider factors,
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3 | * AHB/APBx prescalers and Flash settings
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4 | * @Note This function should be called only once the RCC clock configuration
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5 | * is reset to the default reset state (done in SystemInit() function).
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6 | * @param None
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7 | * @retval None
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8 | */
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9 | static void SetSysClock(void)
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10 | {
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11 | /******************************************************************************/
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12 | /* PLL (clocked by HSE) used as System clock source */
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13 | /******************************************************************************/
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14 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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15 |
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16 | /* Enable HSE */
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17 | RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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18 |
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19 | /* Wait till HSE is ready and if Time out is reached exit */
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20 | do
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21 | {
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22 | HSEStatus = RCC->CR & RCC_CR_HSERDY;
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23 | StartUpCounter++;
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24 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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25 |
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26 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
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27 | {
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28 | HSEStatus = (uint32_t)0x01;
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29 | }
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30 | else
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31 | {
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32 | HSEStatus = (uint32_t)0x00;
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33 | }
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34 |
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35 | if (HSEStatus == (uint32_t)0x01)
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36 | {
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37 | /* Enable high performance mode, System frequency up to 168 MHz */
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38 | RCC->APB1ENR |= RCC_APB1ENR_PWREN;
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39 | PWR->CR |= PWR_CR_PMODE;
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40 |
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41 | /* HCLK = SYSCLK / 1*/
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42 | RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
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43 |
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44 | /* PCLK2 = HCLK / 2*/
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45 | RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
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46 |
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47 | /* PCLK1 = HCLK / 4*/
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48 | RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
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49 |
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50 | /* Configure the main PLL */
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51 | RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
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52 | (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
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53 |
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54 | /* Enable the main PLL */
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55 | RCC->CR |= RCC_CR_PLLON;
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56 |
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57 | /* Wait till the main PLL is ready */
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58 | while((RCC->CR & RCC_CR_PLLRDY) == 0)
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59 | {
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60 | }
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61 |
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62 | /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
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63 | FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
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64 |
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65 | /* Select the main PLL as system clock source */
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66 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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67 | RCC->CFGR |= RCC_CFGR_SW_PLL;
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68 |
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69 | /* Wait till the main PLL is used as system clock source */
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70 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
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71 | {
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72 | }
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73 | }
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74 | else
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75 | { /* If HSE fails to start-up, the application will have wrong clock
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76 | configuration. User can add here some code to deal with this error */
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77 | }
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78 |
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79 | }
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