1 | #include "mac.h"
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2 |
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3 | #include "lpc2468.h"
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4 |
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5 | #include "ucos_ii.h"
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6 | #include "os_cpu.h"
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7 |
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8 | #include "packet.h"
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9 |
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10 |
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11 | static void mac_init_rx_descriptors(void);
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12 |
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13 | static void mac_init_tx_descriptors(void);
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14 |
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15 | static void mac_phy_interrupt(void);
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16 |
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17 | static void mac_interrupt(void);
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18 |
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19 | static void mac_write_phy(INT16U reg, INT16U val);
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20 |
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21 | static INT16U mac_read_phy(INT16U reg);
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22 |
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23 |
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24 | EMAC_DMA_RAM ALIGN static char rx_buffer[MAC_RX_FRAGMENTS][ETH_FRAG_SIZE];
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25 |
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26 | EMAC_DMA_RAM ALIGN static char tx_buffer[MAC_TX_FRAGMENTS][ETH_FRAG_SIZE];
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27 |
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28 | OS_EVENT *tx_pkt_cnt;
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29 |
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30 | EMAC_DMA_RAM static rx_tx_descriptor rx_desc[MAC_RX_FRAGMENTS];
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31 |
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32 | EMAC_DMA_RAM static tstRxStatusDescriptor rx_status_desc[MAC_RX_FRAGMENTS];
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33 |
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34 | EMAC_DMA_RAM static rx_tx_descriptor tx_desc[MAC_TX_FRAGMENTS];
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35 |
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36 | EMAC_DMA_RAM static INT32U tx_status_desc[MAC_TX_FRAGMENTS];
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37 |
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38 |
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39 |
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40 |
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41 | void mac_init(void)
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42 | {
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43 | INT32U dwID;
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44 |
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45 | tx_pkt_cnt = OSSemCreate(1);
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46 |
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47 | AHBCFG2 |= (BIT_17 | BIT_12);
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48 |
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49 | PCONP |= BIT_30; /* power up the mac */
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50 | PINSEL2 |= (BIT_00 | BIT_02 | BIT_08 | /* select the rmii pins */
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51 | BIT_16 | BIT_18 | BIT_20 | BIT_28 | BIT_30);
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52 | PINSEL3 |= (BIT_00 | BIT_02); /* select the mdio and clk pins */
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53 | MAC1 = (BIT_08 | BIT_09 | BIT_10 | BIT_11 | BIT_14 | BIT_15); /* reset mac */
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54 | Command = (BIT_03 | BIT_04 | BIT_05); /* reset the mac */
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55 | MAC1 = 0; /* deassert the soft resets */
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56 | MAC2 = (BIT_04 | BIT_05); /* enable crc and padding */
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57 | IPGR = IPGR_DEFAULT; /* set the back-to-back inter packet gap */
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58 | CLRT = CLRT_DEFAULT; /* set the collision window and retransmission count */
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59 | MAXF = MAX_FRAME; /* maximum frame length */
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60 | MCFG = (BIT_02 | BIT_04 | BIT_15); /* divide host clk by 20 and reset mii */
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61 | MCFG ^= BIT_15; /* deassert the reset from the mii hardware */
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62 | MCMD = 0;
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63 | Command = (BIT_09 | BIT_06); /* enable the rmii and pass runt frames */
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64 | SUPP = BIT_08; /* enable 100MBit mode */
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65 | mac_write_phy(PHY_BCR, BIT_15); /* reset the phy */
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66 | while(mac_read_phy(PHY_BCR) & (BIT_15 | BIT_11)); /* wait until reset done */
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67 | dwID = (mac_read_phy(PHY_ID1) << 16); /* get PHY manufacturer and revision */
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68 | dwID |= (mac_read_phy(PHY_ID2) & 0xFFF0);
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69 | if(dwID != KSZ8001_ID) /* check if this is a KSZ8001L PHY */
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70 | {
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71 | return; /* abort if it's not */
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72 | }
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73 | mac_write_phy(PHY_ICS, BIT_08 | BIT_10); /* enable link interrupt */
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74 | mac_write_phy(PHY_CTL, BIT_14); /* enable the link and act LEDs */
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75 | mac_write_phy(PHY_BCR, BIT_12 | BIT_09); /* enable & start autonegotiation*/
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76 | PINSEL4 |= BIT_22; /* enable EINT1 interrupt */
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77 |
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78 | VICVectPriority15 = 0; /* set up the phy interrupt */
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79 | VICVectAddr15 = (INT32U)mac_phy_interrupt;
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80 | VICIntEnable |= BIT_15; /* enable the link up/down interrupt */
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81 |
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82 | SA0 = (MAC_ADDRESS1 << 8) | MAC_ADDRESS2; /* set up the station address */
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83 | SA1 = (MAC_ADDRESS3 << 8) | MAC_ADDRESS4;
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84 | SA2 = (MAC_ADDRESS5 << 8) | MAC_ADDRESS6;
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85 | RxFilterCtrl = (BIT_02 | BIT_05); /* allow broadcast and perfect */
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86 |
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87 | mac_init_rx_descriptors(); /* initialize rx descriptor table */
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88 | mac_init_tx_descriptors(); /* initialize tx descriptor table */
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89 |
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90 | VICVectPriority21 = 0; /* set up the mac interrupt */
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91 | VICVectAddr21 = (INT32U)mac_interrupt;
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92 | VICIntEnable |= BIT_21; /* enable the mac interrupt */
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93 | IntClear = 0xFFFFFFFF;
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94 | IntEnable = BIT_03 | BIT_07;
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95 |
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96 | return;
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97 | }
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98 |
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99 | void mac_tx_enable(void)
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100 | {
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101 | Command |= BIT_01;
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102 | }
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103 |
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104 | void mac_tx_disable(void)
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105 | {
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106 | Command &= ~BIT_01;
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107 | }
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108 |
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109 | void mac_rx_enable(void)
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110 | {
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111 | Command |= BIT_00;
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112 | MAC1 |=BIT_00;
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113 | }
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114 |
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115 | void mac_rx_disable(void)
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116 | {
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117 | Command &= ~BIT_00;
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118 | MAC1 &= ~BIT_00;
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119 | }
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120 |
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121 | char* mac_new_packet(void)
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122 | {
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123 | INT8U err;
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124 | INT16U idx;
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125 | OSSemPend(tx_pkt_cnt, 0, &err); /* wait until memory is available */
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126 | idx = TxProduceIndex;
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127 | return tx_desc[idx].packet;
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128 | }
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129 |
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130 |
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131 | void mac_send_packet(INT16U size)
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132 | {
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133 | INT16U idx = TxProduceIndex;
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134 | tx_desc[idx].control = (BIT_31 | BIT_30 | (size - 1));
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135 | idx++;
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136 | if(idx == MAC_TX_FRAGMENTS)
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137 | {
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138 | idx = 0;
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139 | }
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140 | TxProduceIndex = idx;
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141 | }
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142 |
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143 |
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144 | static void mac_init_rx_descriptors(void)
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145 | {
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146 | INT16U idx;
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147 | for(idx = 0; idx < MAC_RX_FRAGMENTS; idx++) /* loop for each element */
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148 | {
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149 | rx_desc[idx].packet = &rx_buffer[idx][0]; /* set the buffer pointer */
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150 | rx_desc[idx].control = (BIT_31 | (ETH_FRAG_SIZE - 1)); /* enable rx int */
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151 | rx_status_desc[idx].status = 0; /* zero-out the status and hash fields */
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152 | rx_status_desc[idx].hash = 0;
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153 | }
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154 | RxDescriptor = (INT32U)rx_desc; /* rx descriptor base */
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155 | RxStatus = (INT32U)rx_status_desc; /* status descriptor base */
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156 | RxDescriptorNumber = MAC_RX_FRAGMENTS - 1; /* number of rx descriptors */
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157 | RxConsumeIndex = 0; /* begin at the first rx descriptor */
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158 | }
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159 |
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160 |
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161 | static void mac_init_tx_descriptors(void)
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162 | {
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163 | INT16U idx;
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164 | for(idx = 0; idx < MAC_TX_FRAGMENTS; idx++)
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165 | {
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166 | tx_desc[idx].packet = &tx_buffer[idx][0];
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167 | tx_desc[idx].control = 0;
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168 | }
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169 | TxDescriptor = (INT32U)tx_desc;
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170 | TxStatus = (INT32U)tx_status_desc;
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171 | TxDescriptorNumber = MAC_TX_FRAGMENTS - 1; /* number of tx descriptors */
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172 | TxProduceIndex = 0; /* begin at the first tx descriptor */
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173 | } /* end mac_init_tx_descriptors */
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174 |
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175 |
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176 | /* the phy calls this via external interrupt 1 every time a cable is plugged in or out. */
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177 | static void mac_phy_interrupt(void)
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178 | {
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179 | INT16U interrupt = mac_read_phy(PHY_ICS); /* get the interrupt source */
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180 | if(interrupt & BIT_00)
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181 | {
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182 | INT16U mode = (mac_read_phy(PHY_100BTX) & (BIT_04 | BIT_03 | BIT_02));
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183 | switch(mode)
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184 | {
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185 | case MODE_10M_HALF_DUPLEX:
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186 | {
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187 | MAC2 = (BIT_04 | BIT_05 | BIT_07); /* crc, padding, half duplex */
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188 | SUPP = 0; /* 10MBit mode */
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189 | Command &= ~BIT_10; /* issue half duplex command */
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190 | IPGT = 0x12; /* default setting for 10 MBits, half duplex */
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191 | break;
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192 | }
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193 | case MODE_10M_FULL_DUPLEX:
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194 | {
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195 | MAC2 = (BIT_00 | BIT_04 | BIT_05 | BIT_07); /* crc, padding, full duplex */
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196 | SUPP = 0; /* 10MBit mode */
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197 | Command |= BIT_10; /* issue full-duplex command */
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198 | IPGT = 0x15; /* default setting for 10 MBits, full duplex */
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199 | break;
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200 | }
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201 | case MODE_100M_HALF_DUPLEX:
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202 | {
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203 | MAC2 = (BIT_04 | BIT_05 | BIT_07); /* crc, padding, half duplex */
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204 | SUPP = BIT_08; /* enable 100MBit mode */
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205 | Command &= ~BIT_10; /* issue half-duplex command */
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206 | IPGT = 0x12; /* default setting for 100 MBits, half duplex */
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207 | break;
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208 | }
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209 | case MODE_100M_FULL_DUPLEX:
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210 | {
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211 | MAC2 = (BIT_00 | BIT_04 | BIT_05 | BIT_07); /* crc, padding, full duplex */
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212 | SUPP = BIT_08; /* enable 100MBit mode */
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213 | Command |= BIT_10; /* issue full-duplex command */
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214 | IPGT = 0x15; /* default setting for 100 MBits, full duplex */
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215 | break;
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216 | }
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217 | }
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218 | mac_rx_enable(); /* enable the receiver */
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219 | mac_tx_enable(); /* enable the transmitter */
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220 | }
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221 | else if(interrupt & BIT_02)
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222 | {
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223 | mac_rx_disable(); /* disable the receiver */
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224 | mac_tx_disable(); /* disable the transmitter */
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225 | }
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226 | EXTINT |= BIT_01;
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227 | }
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228 |
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229 |
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230 |
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231 |
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232 |
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233 | static void mac_interrupt(void)
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234 | {
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235 | INT32U int_status = IntStatus; /* get the interrupt source */
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236 | IntClear = int_status; /* acknowledge interrupt */
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237 | int_status &= IntEnable; /* mask out unwanted irq's */
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238 | if(int_status)
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239 | {
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240 | if(int_status & BIT_00) /* rx overrun */
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241 | {
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242 | Command |= BIT_05; /* rx reset */
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243 | }
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244 | if(int_status & BIT_01) /* rx error */
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245 | {
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246 | }
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247 | if(int_status & BIT_02) /* rx finished */
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248 | {
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249 | }
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250 | if(int_status & BIT_03) /* rx done */
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251 | {
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252 |
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253 |
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254 | /* HIER STÜRZT DER KRAM AB */
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255 |
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256 | /*INT16U idx = RxConsumeIndex;
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257 | packet_add(rx_desc[idx].packet, (rx_status_desc[idx].status & 0x7FF));
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258 | idx++;
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259 | if(idx == MAC_RX_FRAGMENTS)
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260 | {
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261 | idx = 0;
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262 | }
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263 | RxConsumeIndex = idx;*/
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264 | }
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265 | if(int_status & BIT_04) /* tx underrun */
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266 | {
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267 | Command |= BIT_04; /* tx reset */
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268 | }
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269 | if(int_status & BIT_05) /* tx error */
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270 | {
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271 | }
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272 | if(int_status & BIT_06) /* tx finished */
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273 | {
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274 | }
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275 | if(int_status & BIT_07) /* tx done */
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276 | {
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277 | OSSemPost(tx_pkt_cnt); /* increase the number of available tx buffers */
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278 | }
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279 | if(int_status & BIT_12) /* software interrupt */
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280 | {
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281 | }
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282 | if(int_status & BIT_13) /* wakeup */
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283 | {
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284 | }
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285 | }
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286 | }
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287 |
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288 | static void mac_write_phy(INT16U reg, INT16U val)
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289 | {
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290 | MADR = (reg & 0x1F); /* the register address. only bits 0..5 are valid. */
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291 | MWTD = val; /* write data */
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292 | while(MIND & BIT_00); /* wait until write cycle is complete */
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293 | }
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294 |
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295 | static INT16U mac_read_phy(INT16U reg)
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296 | {
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297 | MADR = (reg & 0x1F); /* the register address. only bits 0..5 are valid. */
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298 | MCMD = BIT_00; /* issue a read command */
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299 | while(MIND & BIT_00); /* wait until read operation is complete */
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300 | MCMD = 0;
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301 | return MRDD;
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302 | }
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