ISE synthetisiert eine Leitung nicht

library ieee;

use ieee.std_logic_1164.ALL;

use ieee.numeric_std.ALL;

library UNISIM;

use UNISIM.Vcomponents.ALL;

entity wholeDesign is

   port ( clk_24        : in    std_logic; 

          backLight_out : out   std_logic; 

          en_out        : out   std_logic; 

          rs_out        : out   std_logic; 

          rw_out        : out   std_logic; 

          data_out      : inout std_logic_vector (3 downto 0));

end wholeDesign;

architecture BEHAVIORAL of wholeDesign is

   signal XLXN_1                 : std_logic_vector (3 downto 0);

   signal XLXN_2                 : std_logic_vector (7 downto 0);

   signal XLXN_3                 : std_logic;

   signal XLXN_5                 : std_logic;

   signal XLXN_6                 : std_logic;

   signal XLXN_4                 : std_logic;

   component lcdController

      port ( clk_24    : in    std_logic; 

             reset_n   : in    std_logic; 

             posY      : in    std_logic; 

             writeData : in    std_logic; 

             dataIn    : in    std_logic_vector (7 downto 0); 

             posX      : in    std_logic_vector (3 downto 0); 

             ready     : out   std_logic; 

             en        : out   std_logic; 

             rw        : out   std_logic; 

             rs        : out   std_logic; 

             backLight : out   std_logic; 

             data      : inout std_logic_vector (3 downto 0));

   end component;

   component writeText

      port ( clk_24    : in    std_logic; 

             isReady   : in    std_logic; 

             reset_n   : out   std_logic; 

             posY      : out   std_logic; 

             writeData : out   std_logic; 

             char_out  : out   std_logic_vector (7 downto 0); 

             posX      : out   std_logic_vector (3 downto 0));

   end component;

begin

   XLXI_1 : lcdController

      port map (clk_24=>clk_24,

                dataIn(7 downto 0)=>XLXN_2(7 downto 0),

                posX(3 downto 0)=>XLXN_1(3 downto 0),

                posY=> XLXN_4,

                reset_n=>XLXN_5,

                writeData=>XLXN_3,

                backLight=>backLight_out,

                en=>en_out,

                ready=>XLXN_6,

                rs=>rs_out,

                rw=>rw_out,

                data(3 downto 0)=>data_out(3 downto 0));

   XLXI_2 : writeText

      port map (clk_24=>clk_24,

                isReady=>XLXN_6,

                char_out(7 downto 0)=>XLXN_2(7 downto 0),

                posX(3 downto 0)=>XLXN_1(3 downto 0),

                posY => XLXN_4,

                reset_n=>XLXN_5,

                writeData=>XLXN_3);

end BEHAVIORAL;