1 |
void ADC1_Initialize (void)
|
2 |
{
|
3 |
// ADSIDL disabled; ADON enabled;
|
4 |
ADCON1L = (0x8000 & 0x7FFF); //Disabling ADON bit
|
5 |
// FORM Integer; SHRRES 12-bit resolution;
|
6 |
ADCON1H = 0x60;
|
7 |
// PTGEN disabled; SHRADCS 2; REFCIE disabled; SHREISEL Early interrupt is generated 1 TADCORE clock prior to data being ready; REFERCIE disabled; EIEN disabled;
|
8 |
ADCON2L = 0x00;
|
9 |
// SHRSAMC 318;
|
10 |
ADCON2H = 0x13E;
|
11 |
// SWCTRG disabled; SHRSAMP disabled; SUSPEND disabled; SWLCTRG disabled; SUSPCIE disabled; CNVCHSEL AN0; REFSEL disabled;
|
12 |
ADCON3L = 0x00;
|
13 |
// SHREN enabled; C1EN disabled; C0EN disabled; CLKDIV 1; CLKSEL FOSC;
|
14 |
ADCON3H = (0x4080 & 0xFF00); //Disabling C0EN, C1EN, C2EN, C3EN and SHREN bits
|
15 |
// SAMC0EN disabled; SAMC1EN disabled;
|
16 |
ADCON4L = 0x00;
|
17 |
// C0CHS AN0; C1CHS AN1;
|
18 |
ADCON4H = 0x00;
|
19 |
// SIGN0 disabled; SIGN4 disabled; SIGN3 disabled; SIGN2 disabled; SIGN1 disabled; SIGN7 disabled; SIGN6 disabled; DIFF0 disabled; SIGN5 disabled; DIFF1 disabled; DIFF2 disabled; DIFF3 disabled; DIFF4 disabled; DIFF5 disabled; DIFF6 disabled; DIFF7 disabled;
|
20 |
ADMOD0L = 0x00;
|
21 |
// DIFF15 disabled; DIFF14 disabled; SIGN8 disabled; DIFF13 disabled; SIGN14 disabled; DIFF12 disabled; SIGN15 disabled; DIFF11 disabled; DIFF10 disabled; SIGN9 disabled; DIFF8 disabled; DIFF9 disabled; SIGN10 disabled; SIGN11 disabled; SIGN12 disabled; SIGN13 disabled;
|
22 |
ADMOD0H = 0x00;
|
23 |
// DIFF19 disabled; DIFF18 disabled; DIFF17 disabled; DIFF16 disabled; DIFF23 disabled; SIGN16 disabled; DIFF22 disabled; SIGN17 disabled; DIFF21 disabled; SIGN18 disabled; DIFF20 disabled; SIGN19 disabled; SIGN20 disabled; SIGN21 disabled; SIGN22 disabled; SIGN23 disabled;
|
24 |
ADMOD1L = 0x00;
|
25 |
// SIGN24 disabled; DIFF25 disabled; DIFF24 disabled; SIGN25 disabled;
|
26 |
ADMOD1H = 0x00;
|
27 |
// IE15 disabled; IE1 disabled; IE0 disabled; IE3 disabled; IE2 disabled; IE5 disabled; IE4 disabled; IE10 disabled; IE7 disabled; IE6 disabled; IE9 disabled; IE13 disabled; IE8 disabled; IE14 disabled; IE11 disabled; IE12 disabled;
|
28 |
ADIEL = 0x00;
|
29 |
// IE17 disabled; IE18 disabled; IE16 disabled; IE19 disabled; IE20 disabled; IE21 disabled; IE24 enabled; IE25 enabled; IE22 enabled; IE23 disabled;
|
30 |
ADIEH = 0x340;
|
31 |
// CMPEN10 disabled; CMPEN11 disabled; CMPEN6 disabled; CMPEN5 disabled; CMPEN4 disabled; CMPEN3 disabled; CMPEN2 disabled; CMPEN1 disabled; CMPEN0 disabled; CMPEN14 disabled; CMPEN9 disabled; CMPEN15 disabled; CMPEN8 disabled; CMPEN12 disabled; CMPEN7 disabled; CMPEN13 disabled;
|
32 |
ADCMP0ENL = 0x00;
|
33 |
// CMPEN10 disabled; CMPEN11 disabled; CMPEN6 disabled; CMPEN5 disabled; CMPEN4 disabled; CMPEN3 disabled; CMPEN2 disabled; CMPEN1 disabled; CMPEN0 disabled; CMPEN14 disabled; CMPEN9 disabled; CMPEN15 disabled; CMPEN8 disabled; CMPEN12 disabled; CMPEN7 disabled; CMPEN13 disabled;
|
34 |
ADCMP1ENL = 0x00;
|
35 |
// CMPEN10 disabled; CMPEN11 disabled; CMPEN6 disabled; CMPEN5 disabled; CMPEN4 disabled; CMPEN3 disabled; CMPEN2 disabled; CMPEN1 disabled; CMPEN0 disabled; CMPEN14 disabled; CMPEN9 disabled; CMPEN15 disabled; CMPEN8 disabled; CMPEN12 disabled; CMPEN7 disabled; CMPEN13 disabled;
|
36 |
ADCMP2ENL = 0x00;
|
37 |
// CMPEN10 disabled; CMPEN11 disabled; CMPEN6 disabled; CMPEN5 disabled; CMPEN4 disabled; CMPEN3 disabled; CMPEN2 disabled; CMPEN1 disabled; CMPEN0 disabled; CMPEN14 disabled; CMPEN9 disabled; CMPEN15 disabled; CMPEN8 disabled; CMPEN12 disabled; CMPEN7 disabled; CMPEN13 disabled;
|
38 |
ADCMP3ENL = 0x00;
|
39 |
// CMPEN21 disabled; CMPEN22 disabled; CMPEN20 disabled; CMPEN18 disabled; CMPEN19 disabled; CMPEN16 disabled; CMPEN17 disabled; CMPEN25 disabled; CMPEN23 disabled; CMPEN24 disabled;
|
40 |
ADCMP0ENH = 0x00;
|
41 |
// CMPEN21 disabled; CMPEN22 disabled; CMPEN20 disabled; CMPEN18 disabled; CMPEN19 disabled; CMPEN16 disabled; CMPEN17 disabled; CMPEN25 disabled; CMPEN23 disabled; CMPEN24 disabled;
|
42 |
ADCMP1ENH = 0x00;
|
43 |
// CMPEN21 disabled; CMPEN22 disabled; CMPEN20 disabled; CMPEN18 disabled; CMPEN19 disabled; CMPEN16 disabled; CMPEN17 disabled; CMPEN25 disabled; CMPEN23 disabled; CMPEN24 disabled;
|
44 |
ADCMP2ENH = 0x00;
|
45 |
// CMPEN21 disabled; CMPEN22 disabled; CMPEN20 disabled; CMPEN18 disabled; CMPEN19 disabled; CMPEN16 disabled; CMPEN17 disabled; CMPEN25 disabled; CMPEN23 disabled; CMPEN24 disabled;
|
46 |
ADCMP3ENH = 0x00;
|
47 |
// CMPLO 0;
|
48 |
ADCMP0LO = 0x00;
|
49 |
// CMPLO 0;
|
50 |
ADCMP1LO = 0x00;
|
51 |
// CMPLO 0;
|
52 |
ADCMP2LO = 0x00;
|
53 |
// CMPLO 0;
|
54 |
ADCMP3LO = 0x00;
|
55 |
// CMPHI 3;
|
56 |
ADCMP0HI = 0x03;
|
57 |
// CMPHI 0;
|
58 |
ADCMP1HI = 0x00;
|
59 |
// CMPHI 0;
|
60 |
ADCMP2HI = 0x00;
|
61 |
// CMPHI 0;
|
62 |
ADCMP3HI = 0x00;
|
63 |
// OVRSAM 4x; MODE Oversampling Mode; FLCHSEL AN0; IE disabled; FLEN disabled;
|
64 |
ADFL0CON = 0x400;
|
65 |
// OVRSAM 4x; MODE Oversampling Mode; FLCHSEL AN0; IE disabled; FLEN disabled;
|
66 |
ADFL1CON = 0x400;
|
67 |
// OVRSAM 16x; MODE Oversampling Mode; FLCHSEL AN0; IE disabled; FLEN disabled;
|
68 |
ADFL2CON = 0xC00;
|
69 |
// OVRSAM 4x; MODE Oversampling Mode; FLCHSEL AN22; IE disabled; FLEN enabled;
|
70 |
ADFL3CON = 0x8416;
|
71 |
// HIHI disabled; LOLO disabled; HILO disabled; BTWN disabled; LOHI disabled; CMPEN disabled; IE disabled;
|
72 |
ADCMP0CON = 0x00;
|
73 |
// HIHI disabled; LOLO disabled; HILO disabled; BTWN disabled; LOHI disabled; CMPEN disabled; IE disabled;
|
74 |
ADCMP1CON = 0x00;
|
75 |
// HIHI disabled; LOLO disabled; HILO disabled; BTWN disabled; LOHI disabled; CMPEN disabled; IE disabled;
|
76 |
ADCMP2CON = 0x00;
|
77 |
// HIHI disabled; LOLO disabled; HILO disabled; BTWN disabled; LOHI disabled; CMPEN disabled; IE disabled;
|
78 |
ADCMP3CON = 0x00;
|
79 |
// LVLEN9 disabled; LVLEN8 disabled; LVLEN11 disabled; LVLEN7 disabled; LVLEN10 disabled; LVLEN6 disabled; LVLEN13 disabled; LVLEN5 disabled; LVLEN12 disabled; LVLEN4 disabled; LVLEN15 disabled; LVLEN3 disabled; LVLEN14 disabled; LVLEN2 disabled; LVLEN1 disabled; LVLEN0 disabled;
|
80 |
ADLVLTRGL = 0x00;
|
81 |
// LVLEN20 disabled; LVLEN22 disabled; LVLEN21 disabled; LVLEN24 disabled; LVLEN23 disabled; LVLEN25 disabled; LVLEN17 disabled; LVLEN16 disabled; LVLEN19 disabled; LVLEN18 disabled;
|
82 |
ADLVLTRGH = 0x00;
|
83 |
// SAMC 0;
|
84 |
ADCORE0L = 0x00;
|
85 |
// SAMC 0;
|
86 |
ADCORE1L = 0x00;
|
87 |
// RES 12-bit resolution; EISEL Early interrupt is generated 1 TADCORE clock prior to data being ready; ADCS 2;
|
88 |
ADCORE0H = 0x300;
|
89 |
// RES 12-bit resolution; EISEL Early interrupt is generated 1 TADCORE clock prior to data being ready; ADCS 2;
|
90 |
ADCORE1H = 0x300;
|
91 |
// EIEN9 disabled; EIEN7 disabled; EIEN8 disabled; EIEN5 disabled; EIEN6 disabled; EIEN3 disabled; EIEN4 disabled; EIEN1 disabled; EIEN2 disabled; EIEN13 disabled; EIEN0 disabled; EIEN12 disabled; EIEN11 disabled; EIEN10 disabled; EIEN15 disabled; EIEN14 disabled;
|
92 |
ADEIEL = 0x00;
|
93 |
// EIEN17 disabled; EIEN16 disabled; EIEN25 disabled; EIEN19 disabled; EIEN18 disabled; EIEN20 disabled; EIEN24 disabled; EIEN23 disabled; EIEN22 disabled; EIEN21 disabled;
|
94 |
ADEIEH = 0x00;
|
95 |
// C0CIE disabled; C1CIE disabled; SHRCIE disabled; WARMTIME 32768 Source Clock Periods;
|
96 |
ADCON5H = (0xF00 & 0xF0FF); //Disabling WARMTIME bit
|
97 |
|
98 |
//Assign Default Callbacks
|
99 |
ADC1_SetCommonInterruptHandler(&ADC1_CallBack);
|
100 |
ADC1_SetUoutInterruptHandler(&ADC1_Uout_CallBack);
|
101 |
ADC1_Setchannel_AN24InterruptHandler(&ADC1_channel_AN24_CallBack);
|
102 |
ADC1_Setchannel_AN25InterruptHandler(&ADC1_channel_AN25_CallBack);
|
103 |
|
104 |
// Clearing Uout interrupt flag.
|
105 |
IFS7bits.ADCAN22IF = 0;
|
106 |
// Enabling Uout interrupt.
|
107 |
IEC7bits.ADCAN22IE = 1;
|
108 |
// Clearing channel_AN24 interrupt flag.
|
109 |
IFS12bits.ADCAN24IF = 0;
|
110 |
// Enabling channel_AN24 interrupt.
|
111 |
IEC12bits.ADCAN24IE = 1;
|
112 |
// Clearing channel_AN25 interrupt flag.
|
113 |
IFS12bits.ADCAN25IF = 0;
|
114 |
// Enabling channel_AN25 interrupt.
|
115 |
IEC12bits.ADCAN25IE = 1;
|
116 |
|
117 |
// Setting WARMTIME bit
|
118 |
ADCON5Hbits.WARMTIME = 0xF;
|
119 |
// Enabling ADC Module
|
120 |
ADCON1Lbits.ADON = 0x1;
|
121 |
// Enabling Power for the Shared Core
|
122 |
ADC1_SharedCorePowerEnable();
|
123 |
|
124 |
//TRGSRC0 Common Software Trigger; TRGSRC1 None;
|
125 |
ADTRIG0L = 0x01;
|
126 |
//TRGSRC3 None; TRGSRC2 None;
|
127 |
ADTRIG0H = 0x00;
|
128 |
//TRGSRC4 None; TRGSRC5 None;
|
129 |
ADTRIG1L = 0x00;
|
130 |
//TRGSRC6 None; TRGSRC7 None;
|
131 |
ADTRIG1H = 0x00;
|
132 |
//TRGSRC8 None; TRGSRC9 None;
|
133 |
ADTRIG2L = 0x00;
|
134 |
//TRGSRC11 None; TRGSRC10 None;
|
135 |
ADTRIG2H = 0x00;
|
136 |
//TRGSRC13 None; TRGSRC12 None;
|
137 |
ADTRIG3L = 0x00;
|
138 |
//TRGSRC15 None; TRGSRC14 None;
|
139 |
ADTRIG3H = 0x00;
|
140 |
//TRGSRC17 None; TRGSRC16 None;
|
141 |
ADTRIG4L = 0x00;
|
142 |
//TRGSRC19 None; TRGSRC18 None;
|
143 |
ADTRIG4H = 0x00;
|
144 |
//TRGSRC20 None; TRGSRC21 None;
|
145 |
ADTRIG5L = 0x00;
|
146 |
//TRGSRC22 Common Software Trigger; TRGSRC23 None;
|
147 |
ADTRIG5H = 0x01;
|
148 |
//TRGSRC24 Common Software Trigger; TRGSRC25 Common Software Trigger;
|
149 |
ADTRIG6L = 0x101;
|
150 |
}
|