Funktionsabbildung mit Altera Integer Arithmethic Megafunctions

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

LIBRARY lpm;

USE lpm.lpm_components.all;

ENTITY Func IS

PORT(

    x      : in std_logic_vector(7 downto 0);

    reset  : in std_logic;

    clk : in std_logic;

    f      : out std_logic_vector(7 downto 0);

    done   : out std_logic;

    );

END Func;

ARCHITECTURE rtl OF Func IS

--dividierer mit 16 bit zähler und 8bit nenner

component LPM_DIVIDE

    generic (LPM_WIDTHN : natural := 16;

         LPM_WIDTHD : natural := 8;

LPM_NREPRESENTATION : string := "UNSIGNED";

LPM_DREPRESENTATION : string := "UNSIGNED";

LPM_PIPELINE : natural := 0;

LPM_TYPE : string := L_DIVIDE;

LPM_HINT : string := "UNUSED");

port (NUMER : in std_logic_vector(LPM_WIDTHN-1 downto 0);

DENOM : in std_logic_vector(LPM_WIDTHD-1 downto 0);

ACLR : in std_logic := '0';

CLOCK : in std_logic := '0';

CLKEN : in std_logic := '1';

QUOTIENT : out std_logic_vector(LPM_WIDTHN-1 downto 0);

REMAIN : out std_logic_vector(LPM_WIDTHD-1 downto 0));

end component;

component LPM_MULT

    generic ( LPM_WIDTHA : natural := 8;

         LPM_WIDTHB : natural := 8;

         LPM_WIDTHS : natural := 16;

         LPM_WIDTHP : natural := 16;

LPM_REPRESENTATION : string := "UNSIGNED";

LPM_PIPELINE : natural := 0;

LPM_TYPE: string := L_MULT;

LPM_HINT : string := "UNUSED");

port ( DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);

DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);

ACLR : in std_logic := '0';

CLOCK : in std_logic := '0';

CLKEN : in std_logic := '1';

SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0) := (OTHERS

=> '0');

RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));

end component;

type state_t is (S_start, S_calc, S_done);

signal state, state_nxt : state_t;

signal cs_div_res  : std_logic_vector(15 downto 0);

signal cs_mult_res : std_logic_vector(15 downto 0);

signal cs_diff_res : std_logic_vector(7 downto 0);

signal counter : std_logic_vector(7 downto 0);

signal calc : std_logic;

 begin

  cs_mult: LPM_MULT

  port map (

     DATAA  => "11111111",

     DATAB  => cs_diff_res,

     RESULT => cs_mult_res);

  cs_div: LPM_DIVIDE

  port map (

     NUMER    => cs_mult_res,

     DENOM    => "10010110", --150 binär

     QUOTIENT => cs_div_res);

  process(x)

    begin

     cs_diff_res <= std_logic_vector(unsigned(x)-unsigned("110010")); --binär 50

     f <= cd_div_res (7 downto 0); --die ersten 8 least significant bit

  end process;

  process(clk)

  begin

    if clk_in'event and clk_in='1' then

      if reset = '1' then

        counter <= (others => '0');

        state <= S_start;

      end if;         

        state <= state_nxt;

      if calc = '1' then

        counter <= std_logic_vector(unsigned(counter) + 1);

      else

        counter <= (others => '0');

      end if;

    end if;

  end process;

  process(state, counter)

  begin

      --defaultwerte

      state_nxt <= state;

      calc <= '0';

      done <= '0';

      case state is

         when S_start =>

          state_nxt <= S_calc;

         when S_calc =>

          calc='1';

          if counter > 50 then --nach spätestens 50 takten sollte die berechnung fertig sein

            state_nxt <= S_done;

          end if;

         when S_done =>

          done <= '1';

          --idle

      end case;

  end process;

END rtl;