Spartan3 intern RAM mit 4096Byte ->2^12 mit 8 Bit breite

Hallo Leute,

ich bin neu im Bereich der FPGA Programmierung und hab ein kleines
Problem. Ich möche ein internes RAM mit 4096Byte realisieren.
Ich verwende Spartan 3 xc3s200ft256 Starter Kit & Xilinx ISE 7.1 .

Bis jetzt habe ich geschaft 256 Byte zu realisieren2^8, sobald ich
versuche   mehr zu realisieren z.B 2^9 bekomme ich einen Fehler
meldung. und sieht folgendes aus..
   Number of Slice Flip Flops:       4,088 out of   3,840  106%
(OVERMAPPED)
  Number of 4 input LUTs:           2,812 out of   3,840   73%
Logic Distribution:
  Number of occupied Slices:        3,445 out of   1,920
179%(OVERMAPPED).

wie schaffe ich es dass ich 2^12 ohne probleme intern zu realisieren.

vielen dank im Voraus

Code

entity RAM16X8S is
    Port ( WE : in std_logic;
           D : in std_logic_vector(7 downto 0);
           CLK : in std_logic;
           A : in bit_vector(3 downto 0);
           O : out std_logic_vector(7 downto 0));
end RAM16X8S;

architecture Behavioral of RAM16X8S is
type MEM_TYPE is array (15 downto 0) of std_logic_vector(7 downto 0);
begin
P1: process(CLK, WE, A)

  Variable ADR_VAR: integer range 0 to 15;
  Variable MEM: MEM_Type;

  begin

    ADR_Var := conv_integer(to_stdLogicVector(A));


      if (CLK='1' and CLK'event) then
        if WE='1' then
          MEM(ADR_VAR) :=D;
        end if;
      end if;


      O <= MEM(ADR_VAR);
   end process P1;

end Behavioral;
---------------------------------------------------------------
entity ram32 is
    Port ( WE : in std_logic;
           CLK : in std_logic;
           EN : in std_logic;
           A : in bit_vector(3 downto 0);
           DIN : in std_logic_vector(7 downto 0);
           DOUT : out std_logic_vector(7 downto 0));
end ram32;

architecture Behavioral of ram32 is
Signal Dint : std_logic_vector(7 downto 0);
signal WEINT : std_logic;


component RAM16x8s
Port ( WE : in std_logic;
           D : in std_logic_vector(7 downto 0);
           CLK : in std_logic;
           A : in bit_vector(3 downto 0);
           O : out std_logic_vector(7 downto 0));
end component;
begin

WEINT <= WE and EN;

HIGH_Byte2: RAM16X8s
  port map (WE=>WEINT, D=>Din(7 downto 0), CLK=>CLK, A=>A, O=>Dint(7
downto 0));
  Dout <=Dint when EN='1' else (others=>'Z');

end Behavioral;
------------------------------------------------------------------
entity ram is
    Port ( WE : in std_logic;
           CLK : in std_logic;
           A : in bit_vector(8 downto 0);
           Din : in std_logic_vector(7 downto 0);
           Dout : out std_logic_vector(7 downto 0));
end ram;

architecture Behavioral of ram128 is
component ram32
port ( WE : in std_logic;
           CLK : in std_logic;
           EN : in std_logic;
           A : in bit_vector(3 downto 0);
           DIN : in std_logic_vector(7 downto 0);
           DOUT : out std_logic_vector(7 downto 0));
end component;

signal enable: std_logic_vector(63 downto 0);
signal LADR: bit_vector(3 downto 0);
signal HADR: bit_vector(4 downto 0);
begin
 HADR<=A(8 downto 4);
 LADR<=A(3 downto 0);

P1:Process(HADR)
  variable enable_var: std_logic_vector(63 downto 0);
  variable int: integer range 0 to 63;

  begin
    enable_var := (others=>'0');
    INT := conv_integer(To_StdLogicVector(HADR));

    enable_var(int):='1';
    enable <=enable_var;

end process P1;

GEN: for I in 63 downto 0 generate
    RAM_BLOCK: RAM32
    port map(WE,CLK,Enable(I),LADR,Din,Dout);
    end generate;

end Behavioral;