S− sind nur die Soll- Belegung; die Firmware ermittelt die echte Gruppierung. IDAC 1 mA Seite A INA333 MCU umkehrbar T1 F+ V(S+ − S−) GPIO / ADC 100 Ω + TVS MUX SRC Mux-Adressen Quelle → Tx T2 S+ IDAC EN / POL 100 Ω + TVS ADC Vref ADC Vsense MUX SENSE T3 S− Pt100 INA+ / INA− 100 Ω + TVS ADC CM T1..T4
clock pulses for the result of an ADC cycle: SS in, a — — — — — — — r e W A I T t-SU TO- P» 2 OTt N oePA Tz- PP|+AW A I T - S T A T E t ST99 S T A R T 8 6 0 2 2 8 Figure 3.21 If the ADC control is in the WAIT-state a start can be generated and the ADC control starts the UP-phase. The timing of the UP<phase
