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STC12C2052AD-english.pdf
Demo Program(C andASM)..174 7.4.2 Timer 1 Programmable Clock-out on P1.1 and Demo Program(C andASM)..177 7.5 Application note for Timer in practice............................................... 180 Chapter 8. UART with Enhanced Function............................181 8.2 UART Operation Modes .........
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PIC32MX3XX_Data_Sheet.pdf
.................................................................................................. 177 10.0 Direct Memory Access (DMA) Controller ................................................................................................................................. 197 11.0 USB On-The-Go...
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marantz-sr8200-9200-service-manual.pdf
5 OE Output Enable N.C. 10 DQ 12 39 WE Write Enable WE 11 38 DQ 4 RESET 12 MBM29LV400TC/MBM29LV400BC 37 VCC RY/BY Ready/Busy Output N.C. 13 Standard Pinout 36 DQ 11 N.C. 14 DQ 3 35 RESET Hardware Reset Pin/Temporary Sector RY/BY 15 34 DQ 10 Unprotection N.C. 16 33 DQ 2 A17 17 32 DQ 9 BYTE Selects 8-
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DM00031020.pdf
disconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085 Table 177. OTG_FS register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106 Table 178. Core global control and status registers (CSRs). . . . . . . . . . . .
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r_manuel.pdf
disconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085 Table 177. OTG_FS register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106 Table 178. Core global control and status registers (CSRs). . . . . . . . . . . .
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ARTA-user-manual.pdf
5.1 - sets number of channels to mono, stereo or 5.1 multi-channel. Check Boxes FL, FR,, C, LF, BL, BC set which channel in multi-channel stream will contain generated signal (FL – front left, FR – front right, C- centre, BL- back left, BR – back right and LF – low frequency). Signal type section has
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ATmega1284P_128KByte.pdf
synchronous master modes of operation. The description in this section refers to Figure 19-2 on page 177. The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a programmable prescaler or baud rate generator. The down-counter, running at system clock (f osc), is loaded with
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MCU_-_HR8P506_Datasheet_e.pdf
Receive Data Flow....................................................................................177 Preliminary 13/341 Copyright © Shanghai Eastsoft Microelectronics Co., Ltd. http://www.essemi.com HR8P506 Datasheet Figure 5-17 Flowchart of UART0 Data Reception ....................................
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SAM-V71Q-SAM-V71N-SAM-V71J_Datasheet.pdf
Write 0x00000000 (1) 0x00B8 Priority Register A for Slave 7 MATRIX_PRAS7 Read/Write 0x00000222 0x00BC Priority Register B for Slave 7 MATRIX_PRBS7 Read/Write 0x00000000(1) 0x00C0 Priority Register A for Slave 8 MATRIX_PRAS8 Read/Write 0x00000222(1) 0x00C4 Priority Register B for Slave 8 MATRIX_PRBS8
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S32K-RM.pdf
................................ 2039 57.5.35 Tx Broadcast Packets Statistic Register (ENET_RMON_T_BC_PKT)........................................................2039 57.5.36 Tx Multicast Packets Statistic Register (ENET_RMON_T_MC_PKT)........................................................2040 57.5.37
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MC9S08DZ60_Data_Sheet.pdf
INC ,X M ← (M) + 0x01 IX 7C 4 INC oprx8,SP M ← (M) + 0x01 SP1 9E6C ff 6 JMP opr8a – – – – – – DIR BC dd 3 JMP opr16a EXT CC hh ll 4 JMP oprx16,X Jump PC ← Jump Address IX2 DC ee ff 4 JMP oprx8,X IX1 EC ff 3 JMP ,X IX FC 3 JSR opr8a – – – – – – DIR BD dd 5 JSR opr16a PC ← (PC) + n (n = 1, 2, or 3) EXT
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io-controller-hub-9-datasheet.pdf
5.13.10ALT Access Mode.................................................................................. 177 5.13.10.1Write Only Registers with Read Paths in ALT Access Mode ............ 178 5.13.10.2PIC Reserved Bits ................................................................... 180 5.13.10.3Read Only
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H83003H.PDF
group 0 44 H'00B0 to H'00B3 IPRB5 DEND0B 45 H'00B4 to H'00B7 DEND1A 46 H'00B8 to H'00BB DEND1B 47 H'00BC to H'00BF DEND2A DMAC group 1 48 H'00C0 to H'00C3 IPRB4 DEND2B 49 H'00C4 to H'00C7 DEND3A 50 H'00C8 to H'00CB DEND3B 51 H'00CC to H'00CF ERI0 (receive error 0) SCI channel 0 52 H'00D0 to H'00D3 IPRB3
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DSPIC33EP512GM710_datasheet.pdf
8> U3TX – UART3 Transmitter 91 83 0x0000BA IFS5<3> IEC5<3> IPC20<14:12> Reserved 92-94 84-86 0x0000BC-0x0000C0 — — — U4E – UART4 Error Interrupt 95 87 0x0000C2 IFS5<7> IEC5<7> IPC21<14:12> U4RX – UART4 Receiver 96 88 0x0000C4 IFS5<8> IEC5<8> IPC22<2:0> U4TX – UART4 Transmitter 97 89 0x0000C6 IFS5<9>
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stc12c5a60s2-english.pdf
---------------------------- e d . im it END L C U M C S T STC MCU Limited. websit： www.STCMCU.com 177 www.STCMCU.com Mobile:(86)13922809991 Tel:086-755-82948412 Fax:86-755-82905966 6.7.7 Program of PCAInterrupt used to wake up Power Down mode 1. C program /*------------------------------------------
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STC12C5A60S2-english.pdf
---------------------------- e d . im it END L C U M C S T STC MCU Limited. websit： www.STCMCU.com 177 www.STCMCU.com Mobile:(86)13922809991 Tel:086-755-82948412 Fax:86-755-82905966 6.7.7 Program of PCAInterrupt used to wake up Power Down mode 1. C program /*------------------------------------------
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CPU12RM.pdf
Branch if Higher. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 LBHS Long Branch if Higher or Same . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 LBLE Long Branch if Less Than or Equal to Zero . . . . . . . . . . . . . . . . . . . .
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ATMega164_324_644_1284pa.pdf
states depending on mode set by the state of the UMSELn, U2Xn and DDR_XCKn bits. Table 19-1 on page 177 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRRn value for each mode of operation using an internally generated clock source. Note: 1. The baud rate
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HBD855-D_Thyristor_Theory.pdf
. . . . . . . 38 Lamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 AND8007 — Momentary Solid State Switch Using Sensitive Gate SCRs . . . . . . . . . . . . . . . . . . . . 40 for Split Phase Motors . . . . . . . . . . . . . . . . . . . . . . . . . 181 Drivers: Programmable
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STC15-English.pdf
1.10.25 Dimension Drawings of QFN64....................................................................177 1.11 Special Peripheral Function(CCP/SPI,UART1/2/3/4) Switch.........178 1.11.1 Test Porgram that Switch CCP/PWM/PCA(C andASM)..............................180 1.11.2 Test Porgram that Switch PWM2/3
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Atmel-8209-8-bit_AVR_ATmega16M1-32M1-64M1_Datasheet_1_.pdf
compare match on the following timer clock for all compare units. Atmel ATmega16M1/32M1/64M1 [DATASHEET] 177 Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016 16.14.5. Input Capture Register 1 Low and High byte The ICR1L and ICR1H register pair represents the 16-bit value, ICR1.The low byte [7:0]
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doc7707.pdf
writ- ing to the UDRn I/O location. This is the case for both sending and receiving data since the 177 7707F–AVR–11/10 transmitter controls the transfer clock. The data written to UDRn is moved from the transmit buf- fer to the shift register when the shift register is ready to send a new frame. Note
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atmega2560_2561.pdf
the mode of operation selected by the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt. 177 2549I–AVR–07/06 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM22:0)
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mega644.pdf
chronous operation is used, the clock on the XCKn pin will be overridden and used as transmission clock. 177 8011O–AVR–07/10 ATmega164P/324P/644P 16.7.1 Sending Frames with 5 to 8 Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the
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MEGA48V_88V_168V.pdf
(no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. 177 2545T–AVR–05/11 ATmega48/88/168 For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. Assembly code example(1) USART_Init: ; Set baud rate out UBRRnH, r17
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AtMega644P_Datasheet.pdf
hor- izontal arrows illustrate the synchronization variation due to the sampling process. Note the 177 2593O–AVR–02/12 larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (that is, no communication activity).
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ATmegaXX4.pdf
chronous operation is used, the clock on the XCKn pin will be overridden and used as transmission clock. 177 8011G–AVR–08/07 18.7.1 Sending Frames with 5 to 8 Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing
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atmega644.pdf
hor- izontal arrows illustrate the synchronization variation due to the sampling process. Note the 177 2593O–AVR–02/12 larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (that is, no communication activity).
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MC9S12XF512.pdf
2 of 4) Vector Address 1 XGATE 2 Interrupt Source CCR Local Enable Channel ID Mask Vector base + $BC $5E Reserved Vector base + $BA $5D FLASH Fault Detect I bit FCNFG2 (FDIE) Vector base + $B8 $5C FLASH I bit FCNFG (CCIE, CBEIE) Vector base + $B6 $5B CAN wake-up I bit CANRIER (WUPIE) Vector base + $
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MC9S12XF512.pdf
2 of 4) Vector Address 1 XGATE 2 Interrupt Source CCR Local Enable Channel ID Mask Vector base + $BC $5E Reserved Vector base + $BA $5D FLASH Fault Detect I bit FCNFG2 (FDIE) Vector base + $B8 $5C FLASH I bit FCNFG (CCIE, CBEIE) Vector base + $B6 $5B CAN wake-up I bit CANRIER (WUPIE) Vector base + $
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TC1797_UM_v1.1.pdf
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 [1] 12.3.7 Byte Controls, BC[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 [1] 12.3.8 Burst Flash Clock Output/Input, BFCLKO/BFCLKI . . . . . . . . . . . . 12-5 [1] 12.3.9 Wait Input, WAIT . . . .
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ATmega48PA-ATmega88PA-ATmega168PA_Datasheet.pdf
baud; } Note: 1. See Section 6. “About Code Examples” on page 7. ATmega48PA/88PA/168PA [DATASHEET] 177 9223F–AVR–04/14 21.6 Data Transfer Using the USART in MSPI mode requires the transmitter to be enabled, i.e. the TXENn bit in the UCSRnB register is set to one. When the transmitter is enabled, the
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