Suchergebnisse für "when others"

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3880 Treffer für when others Suchergebnisse für "when others"

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  • Datei

    tb_division.vhd

    end if; if cycles mod 3 = 0 then divisor_tvalid_nxt := '0'; else divisor_tvalid_nxt := '1'; end if; when others => -- Test will stop imminently - do nothing null; end case; -- Drive handshake signals with local variable values s_axis_dividend_tvalid <= dividend_tvalid_nxt; s_axis_divisor_tvalid <= divisor_tvalid_nxt; -- Drive AXI slave channel A payload -- Drive 'X's on payload signals when not valid if dividend_tvalid_nxt /= '1' then s_axis_dividend_tdata <= (others => 'X'); else -- TDATA: This holds the dividend operand. It is 24 bits wide and byte-aligned with the operand in the LSBs

    in „Simulation des Divider Generator 3.0“ · FPGA, VHDL & Co. ·

  • Thread

    Umwandlung Verilog / VHDL, kann man das einfacher machen?

    reset : in std_logic := '0'; ReadReg1 : in std_logic_vector(4 downto 0) := (others => '0'); ReadReg2 : in std_logic_vector(4 downto 0) := (others => '0'); WriteReg : in std_logic_vector(4 downto 0) := (others => '0'); WriteData : in std_logic_vector(31 downto

    type reg_t is array (0 to 31) of std_logic_vector(31 downto 0); signal registers : reg_t := (others => (others => '0')); begin -- Sequential (clocked) write. -- 'WriteReg' is the register index to write. 'RegWrite' is the command. process (clock) begin if (rising_edge

    FPGA, VHDL & Co. ·Michael Fischer · ·4 Antworten

  • Datei

    anz5.vhd

    mux_arch of mux is --signal zwmux: STD_LOGIC_VECTOR (3 downto 0); begin mux1 <= reg(15 downto 12) when auson="1000" else reg(11 downto 8) when auson="0100" else reg(7 downto 4) when auson="0010" else reg(3 downto 0); --others zwmux <= "1111"; end mux_arch; --Onehotcounter entity onehot is generic (v1

    in „Fehlermeldung bei Synthese (Ausgabe 7 Segment)“ · FPGA, VHDL & Co. ·

  • Thread

    RAM: warum nicht synthetisierbar?

    #6280347: > Die Tristate Geschichte musst du ausserhalb des Prozesses machen. [vhdl]data_q <= data when ce = '1' and rd = '0' and wr = '1' else (others => 'Z');[/vhdl] Da meckert mir das Radiant: [pre] (VHDL-1576) this construct is only supported in VHDL 1076-2008 [/pre] Habe ich nicht ganz

    deine Arrays kannst du auch mit der folgenden Zeile Code initialisieren: signal cells: ram_t := (others => ( others => '0') );

    FPGA, VHDL & Co. ·Jörg W. · ·43 Antworten

  • Thread

    Multiplikation mit DSP Block auf Cyclone V

    EN2:=EN1; when 3=> IF(Rv<255)THEN R<=STD_LOGIC_VECTOR(to_unsigned(Rv,8)); ELSE R<=(others=>'1'); END IF; DATAVALID<=EN2; when others=> NULL; end case; end loop; [/vhdl] Wie man sieht, ich habe eine Art Pipeline Konstruktion. Das Problem ist jetzt folgendes: manchmal sind die RGB Daten noch nicht bereit, obwohl

    FPGA, VHDL & Co. ·GS · ·3 Antworten

  • Datei

    adc_board.vhd

    RESET => '0' ); -- debugging "lights" led <= addr_adc(7 downto 0); with state select point <= "0001" when IDLE, --1 "0010" when SRREAD, --2 "0100" when SRWRITE, --3 "0000" when others; --0 spp_data <= "10101010"; spp_busy <= '1'; -- clock adc_clock_o <= clk; -- dac config range_sel <= '1'; -- sram config

    in „Multiple Clock Domains“ · FPGA, VHDL & Co. ·

  • Datei

    arctanFP.vhd

    BEGIN IF rising_edge(clk) THEN IF nrst = '0' THEN stateatan <= 0; ce1 <= '0'; nd <= '0'; InpA <= (OTHERS => '0'); InpB <= (OTHERS => '0'); atanFPo <= (OTHERS => '0'); --TestOutp <= (OTHERS => '0'); --(OTHERS => '0'); ELSE CASE stateatan IS WHEN 0 => IF ceatan = '1' THEN InpA <= Xinp; InpB <= Yinp; ce1

    in „Post-Map simulation mit ModelSim“ · FPGA, VHDL & Co. ·

  • Thread

    SRAM wird nicht gelesen vom DE1

    if counter(4) = '0' then sram_io <= "0000000000000111"; else sram_io <= (others => 'Z'); end if; end if; end process; sram_o <= sram_io; end Behavioral; [/vhdl] Danke. Gruss

    musst also zwischen lesen und schreiben unterscheiden. Ganz grob: [vhdl] sram_io <= daten_out when lesenschreiben = '0' else (others => 'Z'); daten_in <= sram_io when lesenschreiben = '1'; [/vhdl] daten_out sind std_logic_vector und zwar die Daten die geschrieben werden sollen, daten_in ist

    FPGA, VHDL & Co. ·Peter B. · ·12 Antworten

  • Thread

    Multiplexer - Problem

    Passend zu deinem ersten Ansatz: [vhdl] data3 <= data1 when sel = '0' else (others=>'Z'); data2 <= data3 when sel = '1' else (others=>'X'); [/vhdl] Bei data2 wird ein Latch verhindert und in der Simulation sollte es auffallen wenn der Pfad im deselektierten

    one_to_two_mux_inout_input is signal data2_i : std_logic_vector(7 downto 0) := "00000000"; begin data3 <= data1 when sel = '0' else "ZZZZZZZZ"; data2 <= data3 when sel = '1' else "ZZZZZZZZ"; end Behavioral; [/vhdl] und synthese funzt super

    FPGA, VHDL & Co. ·Dete Kosschlovsski · ·10 Antworten

  • Thread

    Frequenzteiler

    clock='1' ; count := count+1 ; CASE count IS WHEN 0 => t_clk <= NOT t_clk ; WHEN 2604/2 => t_clk <= NOT t_clk ; WHEN 2604 => count := 0; WHEN OTHERS => NULL ;

    clock='1' ; count := count+1 ; CASE count IS WHEN 0 => t_clk <= NOT t_clk ; WHEN 500000/2 => t_clk <= NOT t_clk ; WHEN 500000 => count := 0; WHEN OTHERS => NULL ;

    FPGA, VHDL & Co. ·Lu Kim · ·5 Antworten

  • Thread

    Probleme beim Verbinden der Signale zwischen zwei Modulen

    z1:zaehler port map(clk, rst, enable, s); p2:process(s) begin case s is when "0000" => display <= "1111110"; when "0001" => display <= "0110000"; when "0010" => display <= "1101101"; when

    when others => display <= "0000001"; end case; end process p2; end bevofsegment; -------------------------------------------------------------------------- ----

    FPGA, VHDL & Co. ·Andre · ·8 Antworten

  • Datei

    i3c2.vhd

    "1101" => delay <= x"2000"; when "1110" => delay <= x"4000"; when others => delay <= x"8000"; end case; when OPCODE_I2C_STOP => bitcount <= unsigned(clk_divide); state <= STATE_I2C_STOP; when OPCODE_NOP => pcnext <= pcnext+1; when others => error <= '1'; end case; end if; when others => state <= STATE_RUN; pcnext <= (others => '0'); skip <= '1'; end case; end if; end process; end Behavioral;

    in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·

  • Thread

    Binär Dividierer: Restoring Methode

    y; two_r <= r&'0'; dif <= two_r - long_y; WITH dif(n) SELECT next_r <= dif(n-1 DOWNTO 0) WHEN '0', two_r(n-1 DOWNTO 0) WHEN OTHERS; remainder_register: PROCESS(clk) BEGIN IF clk'EVENT AND clk = '1' THEN IF load = '1' THEN r <= x; ELSIF update = '1' THEN r <= next_r

    current_state <= 0; ELSIF clk'EVENT AND clk = '1' THEN CASE current_state IS WHEN 0 => IF start = '0' THEN current_state <= 1; END IF; WHEN 1 => IF start = '1' THEN current_state <= 2; END IF; WHEN 2 => current_state <= 3; WHEN 3 => IF count = p-1 THEN

    FPGA, VHDL & Co. ·Lin · ·8 Antworten

  • Thread

    64-Bit breites Datenwort via NIOS II auf Avalon schreiben?

    data_buffer_nxt <= data_buffer; data_valid_nxt <= data_valid; state_nxt <= state; case state is when INIT => avs_s0_waitrequest <= '0'; state_nxt <= IDLE; when IDLE => if (avs_s0_write = '1') then if (avs_s0_address = 0x"01000000") then avs_s0_waitrequest <= '1'; state_nxt <= READ; end if; end if; when READ => avs_s0_waitrequest <= '1'; data_buffer_nxt <= avs_s0_writedata; state_nxt <= READ_WAIT; when READ_WAIT => avs_s0_waitrequest <= '0'; state_nxt <= IDLE

    FPGA, VHDL & Co. ·Largo · ·9 Antworten

  • Thread

    Befehl für keine Signalzuweisung

    zu. In den anderen Cases wird diese Variable nicht verändert. case state is when a => variable_a <= "0001"; when b => variable_a <= variable_a; when others => variable_a <= variable_a; end case; Also ich suche nach etwas wie : variable_a <= null; Also was vom

    Formale richtig wäre z.B.: [vhdl] case state is when a => variable_a <= "0001"; when b => null; when others => null; end case; [/vhdl] Das "null" braucht man, damit irgendetwas in der Zeile steht.

    FPGA, VHDL & Co. ·Helmut · ·6 Antworten

  • Thread

    CPLD - I/O Erweiterung

    ); elsif (A(5 downto 3)="010") then addr_mux2 <= D(2 downto 0); end process; D <= (others => 'Z') when OE='1' else -- hochohmig, wenn nicht gelesen werden soll PA when (A="000000") else PB when (A="000001") else PC when (A="000010") else PD when (A="000011") else (others => '0'); : [/vhdl] EDIT: Stephan M. schrieb im Beitrag #2122085: > Dadurch kann ich beginnen das Layout zu planen > und die Programmierung später angehen. Leg das WR-Signal auf einen Takteingang

    FPGA, VHDL & Co. ·Stephan M. · ·10 Antworten

  • Thread

    Einfacher Bus Multiplexer

    i in 0 to (g_memory_map'length - 1) generate ... x_wb_master_o.dat <= x_wb_slave_array_i(i).dat when s_cs_vector(i) = '1' else (others => 'Z'); ... end generate; [/vhdl] Funktioniert in der Simu super, aber ich mag kein 'Z' für Sachen, die im FPGA laufen. Alternativ habe ich mir das überlegt:

    ... x_wb_master(i) <= x_wb_slave_array_i(i).dat when s_cs_vector(i) = '1' else (others => '0'); ... end generate; x_wb_master_o.dat <= x_wb_master(0) or x_wb_master(1) or .. [/vhdl] Hat natürlich das gleiche fiese Verhalten wie der Z-Bus. Wenn

    FPGA, VHDL & Co. ·Achim · ·6 Antworten

  • Thread

    Probleme mit Signalgenerator

    clk : in std_logic; -- Systemclock (50 MHz) microsteps : in unsigned(31 downto 0) := (others => '0'); -- Anzahl der Schritte, in die die Wellenform unterteilt wird cnt_check : in unsigned(31 downto 0) := (others => '0'); run : in unsigned(31 downto 0) := (others =>

    unsigned(31 downto 0) := (others => '0'); -- Regelung: 0 = nein, 1 = ja rechteck : out std_logic_vector(15 downto 0) := (others => '0'); saegezahn : out std_logic_vector(15 downto 0) := (others => '0');

    FPGA, VHDL & Co. ·Tom · ·53 Antworten

  • Thread

    Fehler in der Übertragung

    process begin wait until falling_edge(main_clk); case FSM1 is when idle => if (dummy=15) then FSM1 <= Data0; intdb0 <= intdb0 + '1'; end if; wrreq <= '0'; when Data0 => FSM1 <= Data1; intdb0 <= intdb0 + '1'; DCFIFO <= intdb0; wrreq <= '1'; when Data1 => FSM1 <= idle; DCFIFO <= intdb0; wrreq <= '1'; when others => null; end case; end process; [/vhdl] Bzgl deiner vermutung hatte ich auch schon die

    FPGA, VHDL & Co. ·Lassmiranda Densiwillja · ·19 Antworten

  • Thread

    Bedingte Zuweisung in Port Map

    der Port Map hinkriegen. Probiert habe ich sowas wie [vhdl]A: Addierer port map(AV(i),BV(i),'0' when i=0 else CV(i),ErgebnisV(i),CV(i+1));[/vhdl] in verschiedenen Varianten. Das scheint nicht zu funktionieren. Beim when wird immer ein Fehler angezeigt. [Natürlich geht es über loop 1 to Breite-1

    > [vhdl]A: Addierer port map(AV(i),BV(i),'0' when i=0 else > CV(i),ErgebnisV(i),CV(i+1));[/vhdl] verständlichere Signalnamen als AV, BV und CV sind sinnvoller als jede elegant anmutende Syntaxverrenkung. SCNR,

    FPGA, VHDL & Co. ·Dussel · ·25 Antworten

  • Datei

    code.vhd

    bitisset : STD_LOGIC_VECTOR(255 downto 0); begin index := 0; bitisset := BITISSETxC; STATExDN <= (others => (others => '0')); CExC <= (others => '0'); BITISSETCExC <= '0'; BITISSETIxC <= (others => '0'); --insert statements to decode internal output signals --below is simple example if state = st3_proc

    in „Komischer Fehler: ERROR:HDLCompiler:463 - "../Huffman.vhd" Line 170“ · FPGA, VHDL & Co. ·

  • Datei

    nibble_data.vhd

    when x"8A3" => counter <= (others => '0'); busy <= '0'; --flag_full2 <= '0'; -- -- MIT LOOP EINFÜGEN der Daten!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! -- when others => --data <= "0000"; -- if counter

    in „VHDL 95% LUTs, wieso so viele?“ · FPGA, VHDL & Co. ·

  • Thread

    Toggle FF

    FF_INPUT: std_logic; begin KOMB: process(DATA_IN, NRZI_INT) begin case DATA_IN is when '1' => FF_INPUT <= NRZI_INT; when others => FF_INPUT <= DATA_IN xnor NRZI_INT; end case; end process KOMB; DFF: process (CLK, DATA_IN) begin if CLK'event and CLK = '1' then NRZI_INT

    Mir kommt diese Zeile sehr komisch vor: when others => FF_INPUT <= DATA_IN xnor NRZI_INT; probier lieber mal: when others => FF_INPUT <= not NRZI_INT; Viele Grüße TobiFlex

    FPGA, VHDL & Co. ·T.M. · ·3 Antworten

  • Thread

    Tasteneingabe mittels Erweiterungsboard?!

    state, toest, seg3, seg2, seg1, seg0) begin -- process Multiplexer case state is when "100" => iobus_b <= leds; when "010" => iobus_b <= seg3; when "110" => iobus_b <= seg2; when "001" => iobus_b <= seg1; when "101" => iobus_b <= seg0; when others => iobus_b <= (others => 'Z'); end case; end process Multiplexer; -- purpose: FlipFlop for the buttons -- type : sequential -- inputs : precount, reset_n -- outputs: buttons buttons_FF: process

    FPGA, VHDL & Co. ·Harry · ·1 Antworten

  • Thread

    SRAM - wieso bekomm ich warnungen ?

    sram 1 oder sram 2 sram_1_io <= write_dat_1; -- Daten schreiben sram_2_io <= (others => 'Z'); else sram_1_ce <= '1'; -- Sram 2 sram_2_ce <= '0'; sram_1_io <= (others => 'Z');-- Daten schreiben sram_2_io <= write_dat_1; end

    sram_2_ce <= '0'; end if; end if; end process; sram_1_io <= write_dat_1 when (write_sel_1='0' and write_wrt_1='1') else (others => 'Z'); sram_1_io <= write_dat_1 when (write_sel_1='1' and write_wrt_1='1') else (others => 'Z'); [/vhdl] BTW: >-- IO auf Treestate

    FPGA, VHDL & Co. ·Michael Sauron · ·5 Antworten

  • Thread

    LSC Smart Connect - neues Smart Home System bei Action

    GPIO0, GPIO2 and GPIO15. I didn’t add any resistors but I had to pull GPIO15 low (as I did before when flashing. Best Jan

    wires them self's are rated for 300V as written in the wire itself. But they do touch each other when leaving the white box.

    Haus & Smart Home ·Jenny P. · ·368 Antworten

  • Datei

    vga_controller.vhd

    -------- -- horizontal and vertical counters signal hcounter : std_logic_vector(10 downto 0) := (others => '0'); signal vcounter : std_logic_vector(10 downto 0) := (others => '0'); -- active when inside visible screen area. signal video_enable: std_logic; begin -- output horizontal and vertical counters

    in „VGA Controller VHDL Speicheranbindung“ · FPGA, VHDL & Co. ·

  • Datei

    pseuzufgen.vhd

    <= 6; when "0110" => NUMBER_OF_REGS <= 7; when "0111" => NUMBER_OF_REGS <= 8; when "1000" => NUMBER_OF_REGS <= 9; when "1001" => NUMBER_OF_REGS <= 10; when "1010" => NUMBER_OF_REGS <= 11; when "1011" => NUMBER_OF_REGS <= 12; when "1100" => NUMBER_OF_REGS <= 13; when "1101" => NUMBER_OF_REGS <= 14; when others => NUMBER_OF_REGS <= 15; end case; end process NUMB_REGISTERS; P1: process(CLK, RESET) begin if RESET = '0' then -- low

    in „flexibler Pseudozufallszahlengenerator! was mache ich falsch?“ · FPGA, VHDL & Co. ·

  • Thread

    Merkwürdiges Verhalten mit diesem VHDL-Programm.

    terminal_count <= '1'; count <= (others => '0'); else terminal_count <= '0'; end if; end process; process begin wait until rising_edge(clk); if terminal_count = '1' then case state is when "01" => state <= "10"; when "10" => state <= "01"; when others => state <= "01"; end case

    FPGA, VHDL & Co. ·Peter B. · ·10 Antworten

  • Datei

    mt48lc16m16a2.vhd

    Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00"; SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); BEGIN -- CS# Decode WITH Cs_n SELECT Cas_in <= TO_BIT (Cas_n, '1') WHEN '0', '1' WHEN '1', '1' WHEN OTHERS; WITH Cs_n SELECT Ras_in <= TO_BIT (Ras_n, '1') WHEN '0', '1' WHEN '1', '1' WHEN OTHERS; WITH Cs_n SELECT We_in <= TO_BIT (We_n, '1') WHEN '0', '1' WHEN '1', '1' WHEN OTHERS; -- Commands Decode Active_enable <= NOT(Ras_in) AND Cas_in AND We_in; Aref_enable

    in „Problem mit vital.timing und vital.primitives“ · FPGA, VHDL & Co. ·

  • Datei

    ALU.vhd

    begin if rising_edge(CLK) then if RST = '1' then COut <= '0'; Z <= '0'; E <= '0'; H <= '0'; Y <= (OTHERS => '0'); elsif CE ='1' then if Oa = Ob then E <= '1'; else E <= '0'; end if; if Oa > Ob then H <= '1'; else H <= '0'; end if; case Sel is when "0000" => Y <= YB; when "0001" => Y <= YAdd(31 downto

    in „Problem mit "Eigenbau" Pipeline ALU“ · FPGA, VHDL & Co. ·

  • Datei

    adc_board.vhd

    "100000000000" then adc_clock <= NOT adc_clock; adc_latency_cntr <= "000000000000"; end if; when "11" => if adc_latency_cntr = "111111111111" then adc_clock <= NOT adc_clock; adc_latency_cntr <= "000000000000"; end if; when others => adc_clock <= clk; end case; end if; end process; ------------

    in „Multiple Clock Domains“ · FPGA, VHDL & Co. ·

  • Thread

    String in std_logic_vector umwandeln

    [vhdl] signal test_byte : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); : test_byte <= constant_bytes'pos(x"A9"); [/vhdl] Das geht sowieso nicht, weil 'pos einen Integer zurückliefert. Und zudem ist 'pos nicht auf solche zusammengesetzten Arrays anwendbar

    Auswahlelement verwenden: [vhdl] if oneofmyfamily=mum then ... case oneofmyfamily is when mum => ... when dad => ... when others => ... end case; [/vhdl] > Das sieht fast so aus wie wenn man ein Enum deklariert: Das ist es eigentlich auch, allerdings sind hier bei VHDL

    FPGA, VHDL & Co. ·Thomas B. · ·9 Antworten

  • Datei

    Lauflicht1.vhd

    downto 8); when "10" => -- disp 3 sseg_anode_data <= "1011"; sseg_data <= xy_data(7 downto 4); when "11" => -- disp 4 sseg_anode_data <= "0111"; sseg_data <= xy_data(3 downto 0); when others => sseg_data <= "1111";

    in „Lauflicht mit Richtungsumkehr“ · FPGA, VHDL & Co. ·

  • Datei

    code.txt

    "; when "0000001111" => res := "1000111"; when others => res := "1111111"; -- nur fuer Simulation end case; return res; end; -- bei groesseren Designs wuerde man die Funktion in ein Package auslagern ------

    in „LED-Multiplex aufm dem Spartan-3 von Digilent“ · FPGA, VHDL & Co. ·

  • Thread

    warning beim Implementieren einer State Machine

    folgezustand <= a_SENDWERT_Z2; -- im Zustand z2 bleiben end if; when others => folgezustand <= zustand; -- zustand nicht verändern end case; end process ue_sn; TxData <= counter; TxPulse <= txflag; end Behavioral

    clk) then zustand <= folgezustand; case folgezustand is -- BITTE BEACHTEN when a_SENDWERT_Z1 => counter <= counter +1 ; txflag <= '0'; when a_SENDWERT_Z2 => txflag <='1'; when others => null end

    FPGA, VHDL & Co. ·befro · ·11 Antworten

  • Thread

    VHDL ERROR 10028

    then var_e <= (var_e +1); end if; state <= ST_B; when others => null; end case; end if; end process H_Counter; V_Counter: process(RESET_n,CLK) -- ______________________ ________ -- ________| VIDEO

    var_s <= (var_s +1); end if; state <= ST_P; when others => null; end case; end if; end process V_Counter; end rtl; [/vhdl] Ich bekomme folgenden Fehler: VHDL Error (10028): Can't resolve multiple constant drivers for net "state.ST_B

    FPGA, VHDL & Co. ·Elvir Ègalo · ·7 Antworten

  • Datei

    max1000_01_test.vhd

    --LED <= Z_DATA(15 downto 8) when USER_BTN = '0' else Z_DATA(7 downto 0); SEN_SDI <= SEN_SDI_buffer3; SEN_SPC <= SEN_SPC_buffer; SEN_SPC_buffer <= SPC_R when state_read = '1' else SPC_WR; SPC_R <= SPI_read_counter(1) when SPI_read_counter

    in „FPGA IoT Maker Board“ · FPGA, VHDL & Co. ·

  • Datei

    gcpu_soc.vhd

    : in std_logic_vector(3 downto 0) := (others => '0'); rs_index : in std_logic_vector(3 downto 0) := (others => '0'); rd : out std_logic_vector(15 downto 0) := (others => '0'); rs : out std_logic_vector(15 downto 0) := (others => '0'); rin : in

    in „ModelSim Problem 'X' anstatt '1' in std_logic_vector signal“ · FPGA, VHDL & Co. ·

  • Datei

    BWS_2011_TFT.vhd

    = '0' when Reset = '0' else DB(1) when (ADR(7 downto 0) = x"11" and IORQ = '0' and WR = '0') else IO11_Latch ; -- Takteingang auf intern VDCLK legen.. VDCLK <= Takt_In ; -- 20Mhz Eingangstakt = VDCLK -- Takterzeugung

    in „ISE erzeugt immerwieder andere JED Datei“ · FPGA, VHDL & Co. ·

  • PDF

    PMOLED_2.4_WHITE_P19706-A01_3PF0MIM9J.pdf

    contains confidential and propNeither it nor the information contained herein shall be disclosed to others or duplicated or used for others without the express written consent of RiTdisplay. http://www.ritdisplay.com REVISION RECORD REV. REVISION DESCRIPTION REV. DATE REMARK X01 INITIAL RELEASE 2012. 11

    in „[V] Ritek OLED Displays 2,4" 128*64 SSD1303“ · Markt ·

  • Thread

    Frage zu fifo

    Pointer. Der läuft kostenlos über: [vhdl] signal wrcnt : unsigned (Addrbreite-1 downto 0) := (others => '0'); signal rdcnt : unsigned (Addrbreite-1 downto 0) := (others => '0'); type speicher is array(0 to (2**Addrbreite)-1) of unsigned(Wortbreite-1 downto 0); signal memory : speicher;

    ; -- Adresse getaktet --> BRAM rdcnt <= rdcnt+1; end if; end process; Full <= '1' when rdcnt = wrcnt+1 else '0'; Empty <= '1' when rdcnt = wrcnt else '0'; end Behavioral; [/vhdl]

    FPGA, VHDL & Co. ·Matze · ·12 Antworten

  • Thread

    Sinus über DDS erzeugen

    signal Result : std_logic_vector (7 downto 0); signal Accum : unsigned (20 downto 0) := (others=>'0'); alias Address : unsigned (5 downto 0) is Accum(Accum'high-2 downto Accum'high-7); alias Sign : std_logic is Accum(Accum'high); -- MSB alias Quadrant : std_logic is Accum(

    Inputs signal clk : std_logic := '0'; signal Freq_Data : std_logic_vector(7 downto 0) := (others => '0'); --Outputs signal Dout : std_logic_vector(7 downto 0); -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test

    FPGA, VHDL & Co. ·Matrix1 · ·66 Antworten

  • Thread

    range Angabe innerhalb von case auch als hexadezimale Zahl möglich?

    vom Standard unterstützt: [vhdl] case to_integer(unsigned(stdlogicvector(19 downto 0))) is when 0 to 4096 => -- ... -- ... when 4097 to ... => -- ... -- ... when others =>

    hexadezimale Zahlen darzustellen. So z.B.: [vhdl] case unsigned(stdlogicvector(19 downto 0)) is when x"0" to x"1000" => -- ... -- ... when others => -- ... end case; [/vhdl] Ist sowas möglich? Vielen Dank im Voraus. zwiepack

    FPGA, VHDL & Co. ·zwiepack · ·4 Antworten

  • Thread

    Altera & ModelSim

    MUX4X1; architecture VERHALTEN of MUX4X1 is begin with S select -- Auswahlsignal Y <= E(0) when "00", E(1) when "01", E(2) when "10", E(3) when "11"; end VERHALTEN;

    Y : out std_logic); end MUX4X1; architecture VERHALTEN of MUX4X1 is begin Y <= E(0) when s = "00" else E(1) when s = "01" else E(2) when s = "10" else E(3) when s = "11"; end VERHALTEN; Ich habe es nur kompiliert und nicht simuliert. Tom

    FPGA, VHDL & Co. ·Peter · ·4 Antworten

  • Thread

    Ein- oder Zwei-Prozess-Darstellung für FSM

    process (state, rst, start, stop, delay, counter) begin next_counter <= (others=>'0'); case state is when reset => next_state <= idle; when idle => if (start='1') then next_state <= work;

    2. begin process begin wait until rising_edge(clk); case state is when reset => counter <= (others=>'0'); state <= idle; when idle => delay <= 0; if (start='1') then

    FPGA, VHDL & Co. ·Manu · ·12 Antworten

  • Thread

    Problem mit CASE Anweisung

    Ich habe folgenden Code, der einen Fehler produziert, wenn ich "others" weglasse. Warum ist das so? [c] CASE counter(3 downto 0) IS WHEN "0000" => output <= out01; select <= sel01; WHEN "0001" => output <= out02; select <= sel02; (weitere cases

    Woher kommt diese Zahl und warum wird das angemahnt? Es gibt doch keine "others", denn der selektierende Vektor ist wirklich nur ein "3 downto 0" Idee ?

    FPGA, VHDL & Co. ·Ratloser · ·4 Antworten

  • Datei

    Uhr.vhd

    (0) <= (others => '0'); if minuten_neu(1) < 5 then minuten_neu(1) <= minuten_neu(1) + 1; else minuten_neu(1) <= (others => '0'); if stunden_neu(0) < 3 then stunden_neu(0) <= stunden_neu(0) + 1; else stunden_neu(0) <= (others => '0'); if stunden_neu(1) < 2 then stunden_neu(1) <= stunden_neu(1) + 1; else stunden_neu(1) <= (others => '0'); end if; -- if stunden_neu(1) end if; -- if stunden_neu(0) end if; -- if minuten_neu

    in „LCD Display scrollt leider“ · FPGA, VHDL & Co. ·

  • Datei

    master2master.vhd

    if Reset = '1' then RX_reg <= (others => '0'); vSCL_M0 := 'U'; vSCL_M1 := 'U'; elsif SYSCLK = '1' and SYSCLK'event then case RX_state is when RX_IDLE => RX_reg <= (others => '0'); when RX_M0toSLA => if SCL_M0 = '1' and vSCL_M0 = '0' then

    in „Master zu Master Kommunikation SPI“ · FPGA, VHDL & Co. ·

  • Datei

    mt46v16m16.vhd

    (OTHERS => '0'); -- Row address mux CASE Bank_addr IS WHEN "00" => Rows_addr := B0_row_addr; WHEN "01" => Rows_addr := B1_row_addr; WHEN "10" => Rows_addr := B2_row_addr; WHEN OTHERS => Rows_addr := B3_row_addr

    in „DDR-RAM in ModelSim“ · FPGA, VHDL & Co. ·