-
PDF
ATmega8.pdf
zero. Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
in „Mikrocontroller und 15'' TFT LCD“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
Roland_G-70_Service_Notes_.pdf
personal data contained in the G-70. There are two modes of updating the Data in the G-70: Mode 1 : by means of a Card It is carried out by means of a card of at least 64 Mbytes and of a PCMCIA adaptor for this card. Mode 2: by means of USB connection. It is carried out by means of a connection USB PC
in „Roland G-70 fährt nicht hoch.“ · Analoge Elektronik und Schaltungstechnik ·
-
PDF
Roland-G-70-Service-Manual.pdf
personal data contained in the G-70. There are two modes of updating the Data in the G-70: Mode 1 : by means of a Card It is carried out by means of a card of at least 64 Mbytes and of a PCMCIA adaptor for this card. Mode 2: by means of USB connection. It is carried out by means of a connection USB PC
in „Roland G-70 fährt nicht hoch.“ · Analoge Elektronik und Schaltungstechnik ·
-
PDF
ATMEGA8_DATENBLATT.pdf
zero. Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
in „I2C/TWI TWBR > 10 warum?“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
SAM-V71Q-SAM-V71N-SAM-V71J_Datasheet.pdf
erased by a Flash erase command or by the ERASE pin. SAM V71 [DATASHEET] 251 Atmel-44003E-ATARM-SAM V71-Datasheet_12-Oct-16 Values written by the user application in the Oscillator Calibration Register (PMC_OCR
in „Atmel SAMV71 CAN FD“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
db_atmega8.pdf
zero. Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
in „ADC-Input und Auswahlverfahren“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
A300_ATMEGA8xxx.pdf
zero. Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
in „atMega8-16 Au beschreiben“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
ATmega32.pdf
0 0 0 See Bit Description Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
in „STK500 als ISP“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
R32C-152_Users_Manual.pdf
Address Reset Value 0 CCR 0004h 0001 1000b Bit Symbol Bit Name Function RW b1 b0 BCD0 0 0 : Divide-by-6 RW Base Clock Divide Ratio 0 1 : Divide-by-4 Select Bit (2) BCD1 1 0 : Divide-by-3 RW 1 1 : Divide-by-2 b3 b2 CCD0 0 0 : Divide-by-4 RW CPU Clock Divide Ratio Select Bit (3) 0 1 : Divide-by-3 CCD1 1 0 : Divide-by-2 RW 1 1 : No division PCD0 b5 b4 RW Peripheral Bus Clock 0 0 : Do not use this combination Divide Ratio Select Bit 0 1 : Divide-by-2 PCD1 (2, 3, 4) 1 0 : Divide-by-3 RW 1 1 : Divide-by-4 — Reserved
in „Keine UART Programmierung bei R32C möglich“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
Infineon_TLE9263QX.pdf
min.) = 0.389 × P_11.3.34 (for worst case at 10.4 kbit/s) V SHS; SAE J2602 Low Slope THDom(min.) = 0.251 × V ; SHS V SHS = 7.6 … 18 V; tbit 96 µs; D4 = tbus_rec(max)/2 tbit; LIN 2.2 Param 30 1) Not subject to production test, specified by design. 2) Not subject to production test, tolerance defined by
in „SBC für CAN/LIN bei einem 24V Bordnetz“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
xc2200_um_v2.1_2008_08_vol2per.pdf
field defines which boundary will be taken as boundary A for the limit checking. 00 The value given by register LCBR0 is selected. B 01B The value given by register LCBR1 is selected. 10B The value given by register LCBR2 is selected. 11B The value given by register LCBR3 is selected. BNDBSEL [3:2] rw
in „Schlechte Datenblätter von Infineon (CAN)“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
sh7020.pdf
selects the refresh mode and the number of wait states during refresh. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or by the standby mode. To prevent RCR from being written incorrectly, it must be written by a different method from most other registers. A
in „welche GPS-Maus ?“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
Atmel-8209-8-bit_AVR_ATmega16M1-32M1-64M1_Datasheet_1_.pdf
CKSEL[3:0] Option External crystal/ceramic Ext osc RC osc 1111 - 1000 resonator PLL output divided by 4 : Ext osc Ext osc 0100 16MHz / PLL driven by external crystal/ceramic resonator PLL output divided by 4 : PLL/4 Ext osc 0101 16MHz / PLL driven by external crystal/ceramic resonator Reserved N/A N/
in „Externer Interrupt“ · Mikrocontroller und Digitale Elektronik ·
-
Datei
t6963c.h
--------------------- * Program to control a T6963C-based 240x64 pixel LCD display * * * * Written by John P. Beale May 3-4, 1997 beale@best.com * * Converted by Nico Sachs Feb. 2006 for AVR-GCC * * Based on information from Steve Lawther, * "Writing Software for T6963C based Graphic LCDs", 1997 which
-
Datei
t6963c.h
--------------------- * Program to control a T6963C-based 240x64 pixel LCD display * * * * Written by John P. Beale May 3-4, 1997 beale@best.com * * Converted by Nico Sachs Feb. 2006 for AVR-GCC * * Based on information from Steve Lawther, * "Writing Software for T6963C based Graphic LCDs", 1997 which
-
PDF
Attiny24a-44a-84a.pdf
bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or written by the CPU. The 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe bits.
in „Kann jemand über meine Inialisierung drüberfliegen?“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
mega644.pdf
0 0 0 See Bit Description Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
in „AVR Controller braucht zu viel Strom“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
MEGA48V_88V_168V.pdf
WDRF: Watchdog system reset flag This bit is set if a watchdog system reset occurs. The bit is reset by a power-on reset, or by writ- ing a logic zero to the flag. Bit 2 – BORF: Brown-out reset flag This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic
in „analog comparator interrupt probleme mit atmegas“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
ATmegaXX4.pdf
0 0 0 See Bit Description Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
in „Atmega644PA Timer3“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
ATMega16.pdf
0 0 0 See Bit Description Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
in „DCF auf INT0“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
SAM3X.pdf
is 0, see “Shift Operations” on page 97. 12.13.3.5 Examples ASR R7, R8, #9 ; Arithmetic shift right by 9 bits LSLS R1, R2, #3 ; Logical shift left by 3 bits with flag update LSR R4, R5, #6 ; Logical shift right by 6 bits ROR R4, R5, R6 ; Rotate right by the value in the bottom byte of R6 RRX R4, R5 ;
in „ARM SAM3x Zähleingang“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
SAM3X.pdf
is 0, see “Shift Operations” on page 97. 12.13.3.5 Examples ASR R7, R8, #9 ; Arithmetic shift right by 9 bits LSLS R1, R2, #3 ; Logical shift left by 3 bits with flag update LSR R4, R5, #6 ; Logical shift right by 6 bits ROR R4, R5, R6 ; Rotate right by the value in the bottom byte of R6 RRX R4, R5 ;
in „Arduino Due: Programmierung ohne 16U2“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
Lenovo_schematic.pdf
PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSION OF R&D SCustomDocument Number Re1.0 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER
in „Pin Belegung bei dem Chip“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
64F3048F16-Hitachi.pdf
bit accumulator by bit manipulation instructions. Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by
in „CPU Melkanlage auslesbar? 64F3059F16“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
ATtiny841_Datasheet.pdf
data is fetched with the POP instruction. It is decremented by two when the return address is put on the stack by a subroutine call or a jump to an interrupt service routine, and incremented by two when data is fetched by a return from subroutine (the RET instruction
in „TOCPMSA1 und TOCPMCOE Verhalten beim Attiny 841“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
ATtiny441_841.pdf
data is fetched with the POP instruction. It is decremented by two when the return address is put on the stack by a subroutine call or a jump to an interrupt service routine, and incremented by two when data is fetched by a return from subroutine (the RET instruction
in „Suche nach ATtiny mit ADC und Gain > 20x“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
ATtiny841_Datasheet.pdf
data is fetched with the POP instruction. It is decremented by two when the return address is put on the stack by a subroutine call or a jump to an interrupt service routine, and incremented by two when data is fetched by a return from subroutine (the RET instruction
in „sleep und Interrupt“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
ATtiny841_Datasheet.pdf
data is fetched with the POP instruction. It is decremented by two when the return address is put on the stack by a subroutine call or a jump to an interrupt service routine, and incremented by two when data is fetched by a return from subroutine (the RET instruction
in „Takt-Vorskalierungsregister beim Attiny841“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
AT90CAN128.pdf
can be done by using the XMMn bits and control by software the most significant bits of the address. By set- ting Port C to output 0x00, and releasing the most significant bits for normal Port Pin operation, the Memory
in „uC + 3 Schieberegister + 7-Segmentanzeige“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
Datasheet_ATmega1281_doc2549.pdf
be done by using the XMMn bits and control by software the most significant bits of the address. By setting Port C to output 0x00, and releas- ing the most significant bits for normal Port Pin operation, the Memory
in „LM73 über TWI/I2C mit Atmega1281 auslesen“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
802.3-2008_section2.pdf
transfer control information and status between the PHY and the STA. Control information is driven by the STA synchronously with respect to MDC and is sampled synchronously by the PHY. Status information is driven by the PHY synchronously with respect to MDC and is sampled synchronously by the STA. MDIO
in „Kommunikation uC mit PHY“ · Analoge Elektronik und Schaltungstechnik ·
-
PDF
atmega2560_2561.pdf
bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
in „Ethernet Buchse“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
LGT8F328P.pdf
map. Stack pointer related to the instruction instruction Stack pointer description PUSH Increase by 1 Data is pushed onto the stack CALL ICALL Increase by 2 The return address of the interrupt or subroutine call is pushed onto the stack RCALL POP Reduced by 1 The data is fetched from the stack RET
in „Neue 8-Bit Tinys vorgestellt: 417/814/816/817“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
2287522.pdf
different values in addition to global programming. Only the 7 least significant bits D[6:0] are affected by the AIF, AI1 and AI0 bits. When the Control register is written, the register entry point determined by D[6:0] is the first register that will be addressed (read or write operation), and can be anywhere
in „[V] 10St. NXP PCA9955 16-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver SSOP28 (10€)“ · Markt ·
-
PDF
2287522.pdf
different values in addition to global programming. Only the 7 least significant bits D[6:0] are affected by the AIF, AI1 and AI0 bits. When the Control register is written, the register entry point determined by D[6:0] is the first register that will be addressed (read or write operation), and can be anywhere
in „[V] 10St. NXP PCA9955 16-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver SSOP28“ · Markt ·
-
PDF
TC1797_UM_v1.1.pdf
= 1024 bytes of memory – Mbyte, MB= 1048576 bytes of memory In general, the k prefix scales a unit by 1000 whereas the K prefix scales a unit by 1024. Hence, the Kbyte unit scales the expression preceding it by 1024. The kBaud unit scales the expression preceding it by 1000. The M prefix scales by 1,000,000
in „TC1797 - keine Datenblätter?“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
doc8209.pdf
PLL input CKSEL3..0 External crystal/ceramic resonator Ext osc RC osc 1111 - 1000 PLL output divided by 4 : 16MHz / PLL driven by externalExt osc Ext osc 0100 crystal/ceramic resonator PLL output divided by 4 : 16MHz / PLL driven by externalPLL/4 Ext osc 0101 crystal/ceramic resonator Reserved N/A N/A
-
PDF
AT90CAN128.pdf
can be done by using the XMMn bits and control by software the most significant bits of the address. By set- ting Port C to output 0x00, and releasing the most significant bits for normal Port Pin operation, the Memory
in „Umrechnen von analog to digital“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
atmel-8393-mcu_wireless-atmega256rfr2-atmega128rfr2-atmega64rfr2_datasheet.pdf
10-84 SCCKDIV Register Bits Register Bits Value Description SCCKDIV2:0 0 Transceiver Clock divided by 256, (62.5kHz) 1 Transceiver Clock divided by 128, (125kHz) 2 Transceiver Clock divided by 64, (250kHz) 3 Transceiver Clock divided by 32, (500kHz) 4 Transceiver Clock divided by 16, (1MHz) 5 Transceiver
in „AVR-Verlustleistung maximieren“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
BFR93AR_1.pdf
1.5 nF 1.5 nF +VCC +VBB L3 10 k L2 1 nF 1 nF 75 L1 270 output 1 nF 75 input DUT 3.3 pF 18 0.68 pF mbb251 L1 = L3 = 5 H choke. L2 = 3 turns 0.4 mm copper wire; winding pitch 1 mm; internal diameter 3 mm. Fig 1. Intermodulation distortion and second harmonic MATV test circuit mra702 mcd087 400 120 P tot
in „KiCAD: SOT323 aus libcms scheint defekt zu sein“ · Platinen ·
-
PDF
scs140--scs146_service_manual.pdf
SCS 146, DESIGN GOAL: Bring the thrill of live performance and movie sound to the home environment by calling on JBL’s professional engineering leadership. SATELLITE TYPE: Titanium-laminate-dometweeter,sealedenclosure SUBWOOFER TYPE: Bass-reflex enclosure PORT DESIGN: FreeFlow™ flared PROFESSIONAL REFERENCE
in „Verständnisfrage HiFi-Verstärker“ · Analoge Elektronik und Schaltungstechnik ·
-
PDF
rej09b0101_16c29hm_2_.pdf
divided by 2 1 012 0 0 0 oscillator divided by 4 1 102 0 0 0 mode (3) divided by 8 1 0 1 0 divided by 16 1 112 0 0 0 On-chip oscillator low power 1 (2) 0 (2) 1 dissipation mode NOTES: 1. When the CM05 bit is set
in „Zeitproblem bei Softwarepwm“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
4620.pdf
Mode” and Section 3.4 “Idle Modes”). as soon as the Reset source has cleared. Execution is clocked by the INTOSC multiplexer driven by the 3.5.1 EXIT BY INTERRUPT internal oscillator block. Execution is clocked by the Any of the available interrupt sources can cause the internal oscillator block until
in „SPI master/slave - schreib/lese befehle ?“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
Mikrocontroller-PIC18F2420.pdf
Mode” and Section 3.4 “Idle Modes”). as soon as the Reset source has cleared. Execution is clocked by the INTOSC multiplexer driven by the inter- 3.5.1 EXIT BY INTERRUPT nal oscillator block. Execution is clocked by the internal Any of the available interrupt sources can cause the oscillator block until
in „Spannungseinbruch beim Sampeln des Signals“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
I-BOTT.PDF
V DD Presence Command ROM Data pulse 8 bits 64 bits Touch 1 1 0 0 1 1 0 0 0 1 1 0 0 Timing defined by host Initiation of time slot (High ▯ Low) defined by host, remaining timing determined by iButton and resistor. LINE TYPE LEGEND: Bus Master Resistor pull–up iButton 081297 7/151 7 V. Memory iButton
in „Design eines hotplugfähigen I2C-Bussystems und Auswahl des Steckverbinders“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
esp32-c3_technical_reference_manual_en.pdf
by setting it to 0. The clock is then divided by a 16-bit prescaler to generate the time-base counter clock (TB_CLK) used by the time-base counter. When the TIMG_T0_DIVIDER field is configured as 2 ~ 65536
in „Mit dem ESP32C3 laufen lernen“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
esp32-c3_technical_reference_manual_en.pdf
by setting it to 0. The clock is then divided by a 16-bit prescaler to generate the time-base counter clock (TB_CLK) used by the time-base counter. When the TIMG_T0_DIVIDER field is configured as 2 ~ 65536
in „ESP32C3 > PLL“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
MC9S12XF512.pdf
Note 2 0 0 Note 3 0 0 1. PORF is set to 1 when a power on reset occurs. Unaffected by system reset. 2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by system reset. 3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on
in „Wie oft kann ein µC programmiert werden?“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
MC9S12XF512.pdf
Note 2 0 0 Note 3 0 0 1. PORF is set to 1 when a power on reset occurs. Unaffected by system reset. 2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by system reset. 3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on
in „Probleme beim Ansteuern eines EEPROM über SPI“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
User_guide_-_Driver.pdf
device and store the values in the FIFO. The application can then periodically drain the FIFO either by polling, or by interrupts, or by using the uDMA controller. A non-blocking read is configured by using the function EPINonBlockingReadCOnfigure(). The read operation is started with EPINonBlockingReadStart
in „PCF8574 mit LM3S8938 per I2C auslesen“ · Mikrocontroller und Digitale Elektronik ·