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PDF
hut1_12v2.pdf
device. The absence of a Dynamic Flag usage implies that the flag is false or the feature defined by the flag is not supported by the device. Dynamic Flags are typically declared in a report as a single-bit field, where a value of 1 returned by the device indicates that the feature is enabled. The assertion
in „USB HID Descriptor Spotify-Steuerung STM32“ · Mikrocontroller und Digitale Elektronik ·
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PDF
UM10398_-_LPC11xx_UserManual.pdf
by the CAN controller. 0 Since this bit was last reset by the CPU, no message has been successfully transmitted. 1 Since this bit was last set to zero by the CPU, a message has been successfully received
in „Cortex-M UART im Polling-Betrieb“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Datasheet_ILI9225DS_V022.pdf
by WDR registe1. 0 1 1 0 Read from the internal GRAM by RDR register. 1 1 0 1 1 Registers selection by the SPI system interface Function R/W RS Write an index to IR register 0 0 Read an internal status
in „STM32F103 TFT SPI ILI9225“ · Mikrocontroller und Digitale Elektronik ·
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PDF
avr-libc-user-manual-1.8.0.pdf
fol- lowed by an exponent. An exponent consists of an ’E’ or ’e’ , followed by an optional plus or minus sign, followed by a sequence of digits. Leading white-space characters in the string are skipped. The strtod
in „Interrupt Probleme beim Arduino“ · Mikrocontroller und Digitale Elektronik ·
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PDF
gps-spec-IS_GPS_200J.pdf
L2 is BPSK modulated by only one of those two bit trains; the bit train to be used for L2 modulation is selected by ground command. A third modulation mode is also selectable on the L2 channel by ground command: it utilizes
in „Magisches Auge für GPS-Empfänger“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Programmer_Manual.pdf
Programmer 2-171 Command Descriptions Syntax PICTBridge:PAPERSIZE { DEFLT | L | L2 | HAGAKIPCARD | MM54BY86 | MM100BY150 | IN4BY6 | IN8BY10 | LETTER | IN11BY17 | A0 | A1 | A2 | A3 | A4 | A5 | A6 | A7 | A8 | A9 | B0 | B1 | B2 | B3 | B4 | B5 | B6 | B7 | B8 | B9 | ROLL89MM | ROLL127MM | ROLL100MM | ROLL210MM
in „Tektronix über R232 auslesen ABER FFT und nicht Waveform“ · Mikrocontroller und Digitale Elektronik ·
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PDF
EN_UM_N32G45x_Series_User_Manual_V3.pdf
not divided 1000: SYSCLK divided by 2 1001: SYSCLK divided by 4 1010: SYSCLK divided by 8 1011: SYSCLK divided by 16 1100: SYSCLK divided by 64 1101: SYSCLK divided by 128 1110: SYSCLK divided by 256 1111: SYSCLK divided by 512 3:2 SCLKSTS
in „ALLPOWERS S2000 PRO Reparaturhilfe“ · Mikrocontroller und Digitale Elektronik ·
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PDF
slau144j.pdf
divided by 1, 2, 4, or 8. MCLK is used by the CPU and system. • SMCLK: Sub-main clock. SMCLK is software selectable as LFXT1CLK, VLOCLK, XT2CLK (if available on-chip), or DCOCLK. SMCLK is divided by 1, 2, 4, or
in „MSP430 Gleitkommazahl in Flash speichern“ · Mikrocontroller und Digitale Elektronik ·
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PDF
family_guide.pdf
divided by 1, 2, 4, or 8. MCLK is used by the CPU and system. • SMCLK: Sub-main clock. SMCLK is software selectable as LFXT1CLK, VLOCLK, XT2CLK (if available on-chip), or DCOCLK. SMCLK is divided by 1, 2, 4, or
in „MSP430 Output nur auf zwei von vier Pinnen möglich?“ · Mikrocontroller und Digitale Elektronik ·
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PDF
at91sam.pdf
: Processor Clock Prescaler PRES Processor Clock 0 0 0 Selected clock 0 0 1 Selected clock divided by 2 0 1 0 Selected clock divided by 4 0 1 1 Selected clock divided by 8 1 0 0 Selected clock divided by 16 1 0 1 Selected clock divided by 32 1 1 0 Selected clock divided by 64 1 1 1 Reserved 199 6120I–ATARM
in „SPI-Initialisierung von zwei Geräte über den gleichen Bus“ · Mikrocontroller und Digitale Elektronik ·
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PDF
SH7709.pdf
not change to the interrupt acceptance level when an interrupt is generated. Initialized to B'1111 by a reset. S bit: Used by the MAC instruction. T bit: Used by the MOVT, CMP/cond, TAS, TST, BT, BF, SETT, CLRT, and DT instructions to indicate true (1) or false (0). Used by the ADDV/C, SUBV/C, DIV0U/
in „HD6417709A F133B“ · Mikrocontroller und Digitale Elektronik ·
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PDF
doc7593.pdf
the USB ID pin). The selected controller is ‘Idle’. The USB Controller can at any time be ‘stopped’ by clearing USBE. In fact, clearing USBE acts as an hardware reset. 251 7593J–AVR–03/09 21.4.3 Interrupts Two interrupts vectors are assigned to USB interface. Figure 21-10. USB Interrupt System USB General
in „Problem mit dem TC4469“ · Mikrocontroller und Digitale Elektronik ·
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PDF
CPU12RM.pdf
Multiplication and Division Instructions Mnemonic Function Operation Multiplication Instructions EMUL 16 by 16 multiply (unsigned) (D) × (Y) ⇒ Y : D EMULS 16 by 16 multiply (signed) (D) × (Y) ⇒ Y : D MUL 8 by 8 multiply (unsigned) (A) × (B) ⇒ A : B Division Instructions EDIV 32 by 16 divide (unsigned) (Y :
in „HCS12 CPU Disassembler“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Roland_G-70_Service_Notes_.pdf
personal data contained in the G-70. There are two modes of updating the Data in the G-70: Mode 1 : by means of a Card It is carried out by means of a card of at least 64 Mbytes and of a PCMCIA adaptor for this card. Mode 2: by means of USB connection. It is carried out by means of a connection USB PC
in „Roland G-70 fährt nicht hoch.“ · Analoge Elektronik und Schaltungstechnik ·
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PDF
Roland-G-70-Service-Manual.pdf
personal data contained in the G-70. There are two modes of updating the Data in the G-70: Mode 1 : by means of a Card It is carried out by means of a card of at least 64 Mbytes and of a PCMCIA adaptor for this card. Mode 2: by means of USB connection. It is carried out by means of a connection USB PC
in „Roland G-70 fährt nicht hoch.“ · Analoge Elektronik und Schaltungstechnik ·
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PDF
ATmega8.pdf
zero. Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
in „Mikrocontroller und 15'' TFT LCD“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATMEGA8_DATENBLATT.pdf
zero. Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
in „I2C/TWI TWBR > 10 warum?“ · Mikrocontroller und Digitale Elektronik ·
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PDF
SAM-V71Q-SAM-V71N-SAM-V71J_Datasheet.pdf
erased by a Flash erase command or by the ERASE pin. SAM V71 [DATASHEET] 251 Atmel-44003E-ATARM-SAM V71-Datasheet_12-Oct-16 Values written by the user application in the Oscillator Calibration Register (PMC_OCR
in „Atmel SAMV71 CAN FD“ · Mikrocontroller und Digitale Elektronik ·
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PDF
db_atmega8.pdf
zero. Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
in „ADC-Input und Auswahlverfahren“ · Mikrocontroller und Digitale Elektronik ·
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PDF
A300_ATMEGA8xxx.pdf
zero. Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
in „atMega8-16 Au beschreiben“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATmega32.pdf
0 0 0 See Bit Description Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
in „STK500 als ISP“ · Mikrocontroller und Digitale Elektronik ·
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PDF
R32C-152_Users_Manual.pdf
Address Reset Value 0 CCR 0004h 0001 1000b Bit Symbol Bit Name Function RW b1 b0 BCD0 0 0 : Divide-by-6 RW Base Clock Divide Ratio 0 1 : Divide-by-4 Select Bit (2) BCD1 1 0 : Divide-by-3 RW 1 1 : Divide-by-2 b3 b2 CCD0 0 0 : Divide-by-4 RW CPU Clock Divide Ratio Select Bit (3) 0 1 : Divide-by-3 CCD1 1 0 : Divide-by-2 RW 1 1 : No division PCD0 b5 b4 RW Peripheral Bus Clock 0 0 : Do not use this combination Divide Ratio Select Bit 0 1 : Divide-by-2 PCD1 (2, 3, 4) 1 0 : Divide-by-3 RW 1 1 : Divide-by-4 — Reserved
in „Keine UART Programmierung bei R32C möglich“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Infineon_TLE9263QX.pdf
min.) = 0.389 × P_11.3.34 (for worst case at 10.4 kbit/s) V SHS; SAE J2602 Low Slope THDom(min.) = 0.251 × V ; SHS V SHS = 7.6 … 18 V; tbit 96 µs; D4 = tbus_rec(max)/2 tbit; LIN 2.2 Param 30 1) Not subject to production test, specified by design. 2) Not subject to production test, tolerance defined by
in „SBC für CAN/LIN bei einem 24V Bordnetz“ · Mikrocontroller und Digitale Elektronik ·
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PDF
xc2200_um_v2.1_2008_08_vol2per.pdf
field defines which boundary will be taken as boundary A for the limit checking. 00 The value given by register LCBR0 is selected. B 01B The value given by register LCBR1 is selected. 10B The value given by register LCBR2 is selected. 11B The value given by register LCBR3 is selected. BNDBSEL [3:2] rw
in „Schlechte Datenblätter von Infineon (CAN)“ · Mikrocontroller und Digitale Elektronik ·
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PDF
sh7020.pdf
selects the refresh mode and the number of wait states during refresh. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or by the standby mode. To prevent RCR from being written incorrectly, it must be written by a different method from most other registers. A
in „welche GPS-Maus ?“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Atmel-8209-8-bit_AVR_ATmega16M1-32M1-64M1_Datasheet_1_.pdf
CKSEL[3:0] Option External crystal/ceramic Ext osc RC osc 1111 - 1000 resonator PLL output divided by 4 : Ext osc Ext osc 0100 16MHz / PLL driven by external crystal/ceramic resonator PLL output divided by 4 : PLL/4 Ext osc 0101 16MHz / PLL driven by external crystal/ceramic resonator Reserved N/A N/
in „Externer Interrupt“ · Mikrocontroller und Digitale Elektronik ·
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Datei
t6963c.h
--------------------- * Program to control a T6963C-based 240x64 pixel LCD display * * * * Written by John P. Beale May 3-4, 1997 beale@best.com * * Converted by Nico Sachs Feb. 2006 for AVR-GCC * * Based on information from Steve Lawther, * "Writing Software for T6963C based Graphic LCDs", 1997 which
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Datei
t6963c.h
--------------------- * Program to control a T6963C-based 240x64 pixel LCD display * * * * Written by John P. Beale May 3-4, 1997 beale@best.com * * Converted by Nico Sachs Feb. 2006 for AVR-GCC * * Based on information from Steve Lawther, * "Writing Software for T6963C based Graphic LCDs", 1997 which
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PDF
Attiny24a-44a-84a.pdf
bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or written by the CPU. The 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe bits.
in „Kann jemand über meine Inialisierung drüberfliegen?“ · Mikrocontroller und Digitale Elektronik ·
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PDF
mega644.pdf
0 0 0 See Bit Description Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
in „AVR Controller braucht zu viel Strom“ · Mikrocontroller und Digitale Elektronik ·
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PDF
MEGA48V_88V_168V.pdf
WDRF: Watchdog system reset flag This bit is set if a watchdog system reset occurs. The bit is reset by a power-on reset, or by writ- ing a logic zero to the flag. Bit 2 – BORF: Brown-out reset flag This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic
in „analog comparator interrupt probleme mit atmegas“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATmegaXX4.pdf
0 0 0 See Bit Description Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
in „Atmega644PA Timer3“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATMega16.pdf
0 0 0 See Bit Description Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
in „DCF auf INT0“ · Mikrocontroller und Digitale Elektronik ·
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PDF
SAM3X.pdf
is 0, see “Shift Operations” on page 97. 12.13.3.5 Examples ASR R7, R8, #9 ; Arithmetic shift right by 9 bits LSLS R1, R2, #3 ; Logical shift left by 3 bits with flag update LSR R4, R5, #6 ; Logical shift right by 6 bits ROR R4, R5, R6 ; Rotate right by the value in the bottom byte of R6 RRX R4, R5 ;
in „ARM SAM3x Zähleingang“ · Mikrocontroller und Digitale Elektronik ·
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PDF
SAM3X.pdf
is 0, see “Shift Operations” on page 97. 12.13.3.5 Examples ASR R7, R8, #9 ; Arithmetic shift right by 9 bits LSLS R1, R2, #3 ; Logical shift left by 3 bits with flag update LSR R4, R5, #6 ; Logical shift right by 6 bits ROR R4, R5, R6 ; Rotate right by the value in the bottom byte of R6 RRX R4, R5 ;
in „Arduino Due: Programmierung ohne 16U2“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Lenovo_schematic.pdf
PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSION OF R&D SCustomDocument Number Re1.0 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER
in „Pin Belegung bei dem Chip“ · Mikrocontroller und Digitale Elektronik ·
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PDF
64F3048F16-Hitachi.pdf
bit accumulator by bit manipulation instructions. Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by
in „CPU Melkanlage auslesbar? 64F3059F16“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATtiny841_Datasheet.pdf
data is fetched with the POP instruction. It is decremented by two when the return address is put on the stack by a subroutine call or a jump to an interrupt service routine, and incremented by two when data is fetched by a return from subroutine (the RET instruction
in „TOCPMSA1 und TOCPMCOE Verhalten beim Attiny 841“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATtiny441_841.pdf
data is fetched with the POP instruction. It is decremented by two when the return address is put on the stack by a subroutine call or a jump to an interrupt service routine, and incremented by two when data is fetched by a return from subroutine (the RET instruction
in „Suche nach ATtiny mit ADC und Gain > 20x“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATtiny841_Datasheet.pdf
data is fetched with the POP instruction. It is decremented by two when the return address is put on the stack by a subroutine call or a jump to an interrupt service routine, and incremented by two when data is fetched by a return from subroutine (the RET instruction
in „sleep und Interrupt“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATtiny841_Datasheet.pdf
data is fetched with the POP instruction. It is decremented by two when the return address is put on the stack by a subroutine call or a jump to an interrupt service routine, and incremented by two when data is fetched by a return from subroutine (the RET instruction
in „Takt-Vorskalierungsregister beim Attiny841“ · Mikrocontroller und Digitale Elektronik ·
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PDF
AT90CAN128.pdf
can be done by using the XMMn bits and control by software the most significant bits of the address. By set- ting Port C to output 0x00, and releasing the most significant bits for normal Port Pin operation, the Memory
in „uC + 3 Schieberegister + 7-Segmentanzeige“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Datasheet_ATmega1281_doc2549.pdf
be done by using the XMMn bits and control by software the most significant bits of the address. By setting Port C to output 0x00, and releas- ing the most significant bits for normal Port Pin operation, the Memory
in „LM73 über TWI/I2C mit Atmega1281 auslesen“ · Mikrocontroller und Digitale Elektronik ·
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PDF
802.3-2008_section2.pdf
transfer control information and status between the PHY and the STA. Control information is driven by the STA synchronously with respect to MDC and is sampled synchronously by the PHY. Status information is driven by the PHY synchronously with respect to MDC and is sampled synchronously by the STA. MDIO
in „Kommunikation uC mit PHY“ · Analoge Elektronik und Schaltungstechnik ·
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PDF
atmega2560_2561.pdf
bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
in „Ethernet Buchse“ · Mikrocontroller und Digitale Elektronik ·
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PDF
LGT8F328P.pdf
map. Stack pointer related to the instruction instruction Stack pointer description PUSH Increase by 1 Data is pushed onto the stack CALL ICALL Increase by 2 The return address of the interrupt or subroutine call is pushed onto the stack RCALL POP Reduced by 1 The data is fetched from the stack RET
in „Neue 8-Bit Tinys vorgestellt: 417/814/816/817“ · Mikrocontroller und Digitale Elektronik ·
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PDF
2287522.pdf
different values in addition to global programming. Only the 7 least significant bits D[6:0] are affected by the AIF, AI1 and AI0 bits. When the Control register is written, the register entry point determined by D[6:0] is the first register that will be addressed (read or write operation), and can be anywhere
in „[V] 10St. NXP PCA9955 16-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver SSOP28 (10€)“ · Markt ·
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PDF
2287522.pdf
different values in addition to global programming. Only the 7 least significant bits D[6:0] are affected by the AIF, AI1 and AI0 bits. When the Control register is written, the register entry point determined by D[6:0] is the first register that will be addressed (read or write operation), and can be anywhere
in „[V] 10St. NXP PCA9955 16-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver SSOP28“ · Markt ·
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PDF
TC1797_UM_v1.1.pdf
= 1024 bytes of memory – Mbyte, MB= 1048576 bytes of memory In general, the k prefix scales a unit by 1000 whereas the K prefix scales a unit by 1024. Hence, the Kbyte unit scales the expression preceding it by 1024. The kBaud unit scales the expression preceding it by 1000. The M prefix scales by 1,000,000
in „TC1797 - keine Datenblätter?“ · Mikrocontroller und Digitale Elektronik ·
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PDF
doc8209.pdf
PLL input CKSEL3..0 External crystal/ceramic resonator Ext osc RC osc 1111 - 1000 PLL output divided by 4 : 16MHz / PLL driven by externalExt osc Ext osc 0100 crystal/ceramic resonator PLL output divided by 4 : 16MHz / PLL driven by externalPLL/4 Ext osc 0101 crystal/ceramic resonator Reserved N/A N/A