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PDF
AT90CAN128.pdf
200 75 % 0.250 20 8 6 5 1 0x04 0x0E 0x4B 0.416666 12 5 3 3 1 0x08 0x08 0x25 0.500 16 7 4 4 1 0x0A 0x0C 0x37 125 75 % 1.000 8 3 2 2 1 0x16 0x04 0x13 0.500 20 8 6 5 1 0x0A 0x0E 0x4B 100 75 % 0.833333 12 5 3 3 1 0x12 0x08 0x25 (1) x - - - n o d a t a - - - 1000 63 % 0.125
in „Umrechnen von analog to digital“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Atiny2313.pdf
. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized exter- nal components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the
in „Suche tutorial“ · Mikrocontroller und Digitale Elektronik ·
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PDF
1_AMD_BKDG_Family__15h_Mod_00h-0Fh_BKDG.pdf
0700 0007 0707 07BB 07E5 07CA 07B0 0758 0711 072C 0740 BB07 E507 CA07 B007 5807 1107 2C07 DD06 4007 08 0800 0008 0808 0804 0802 0801 0867 088B 08CE 08FD 085D 0408 0208 0108 6708 8B08 CE08 FD08 5D08 09 0900 0009 0909 09BC 095E 092F 09A1 09E8 0933 0974 09C0 BC09 5E09 2F09 A109 E809 3309 7409 C009 0A 0A00
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ATmega48PA-ATmega88PA-ATmega168PA_Datasheet.pdf
Ext I/O Registers0x0060 - 0x00FF 0x0100 Internal SRAM (512/1024/1024/2048 x 8) 0x02FF/0x04FF/0x4FF/0x08FF ATmega48PA/88PA/168PA [DATASHEET] 17 9223F–AVR–04/14 8.3.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access
in „Probleme mit Int Capt ISR ATmega48PA“ · Mikrocontroller und Digitale Elektronik ·
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PDF
datasheet.pdf
Target Speed Register - Index 07h (Bank 0).............. 61 8.11 SYSFANOUT Stop Value Register - Index 08h (Bank 0)..................................................... 62 8.12 CPUFANOUT0 Stop Value Register - Index 09h (Bank 0)...................................................62 8.13 SYSFANOUT Start-up
in „(Windows/Winbond) CPU Temperatur auslesen“ · Mikrocontroller und Digitale Elektronik ·
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PDF
BME680.pdf
1.4 s (brand-new sensors) τ33-63% Continuous mode 0.75 s Resolution of gas sensor resistance 0.05 0.08 0.11 % measurement Noise in gas sensor NR 1.5 % resistance (RMS) 1The sensors are electrically operable within this range. Actual performance may vary 2Response time of unsoldered, brand-new sensors
in „PIR-Sensor wird von BME680 gestört, warum?“ · Mikrocontroller und Digitale Elektronik ·
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PDF
BME680.pdf
1.4 s (brand-new sensors) τ33-63% Continuous mode 0.75 s Resolution of gas sensor resistance 0.05 0.08 0.11 % measurement Noise in gas sensor NR 1.5 % resistance (RMS) 1The sensors are electrically operable within this range. Actual performance may vary 2Response time of unsoldered, brand-new sensors
in „BME680 Berechnung Temperatur Luftfeuchtigkeit Druck Gas Fragen Initialisierung Assembler ASM ATmega8“ · Mikrocontroller und Digitale Elektronik ·
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PDF
STM8_Programming_Manual.pdf
input fMASTER Timer A-TI1 Timer A-CEN = CNT_EN Timer A-CK_PSC Timer A-CNT 00 01 02 03 04 05 06 07 08 09 Timer A-TIF Timer B-CEN = CNT_EN Timer B-CK_PSC Timer B-CNT 00 01 02 03 04 05 06 07 08 09 Timer B-TIF 17.5 TIM1 capture/compare channels The timer I/O pins (TIM1_CCi) can be configured either for
in „STLINK V2 und China Boards“ · Mikrocontroller und Digitale Elektronik ·
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PDF
mb1045_changed.pdf
N0PA4 PA3 PC3 P0U3A0N5 N0PC4 MIC_CK N0PD4 PD3 PG3 P0U3B0N12 N0PG4 N0A14 VBUS_FS1 P0R26602 P0R26601 PA9 DAC_OUT1 PA4 N4 P0U3A0PA4 PC4 5 PC4 PC8 P0R28002 P0R28001 MC_WH0WH FMC_NOE0FMC0NOE PD4 D11 P0U3B0PD4 PG4 12 R28P0R28601 P0R28602 PG4 A14 PA10 DAC_OUT2 PA50PA5 P4 P0U3A0P4 P0U3A0P5 5 PC50PC5 PC8 R281 0 P03P503
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PDF
mb1045_changed_korrigiert.pdf
N0PA4 PA3 PC3 P0U3A0N5 N0PC4 MIC_CK N0PD4 PD3 PG3 P0U3B0N12 N0PG4 N0A14 VBUS_FS1 P0R26602 P0R26601 PA9 DAC_OUT1 PA4 N4 P0U3A0PA4 PC4 5 PC4 PC8 P0R28002 P0R28001 MC_WH0WH FMC_NOE0FMC0NOE PD4 D11 P0U3B0PD4 PG4 12 R28P0R28601 P0R28602 PG4 A14 PA10 DAC_OUT2 PA50PA5 P4 P0U3A0P4 P0U3A0P5 5 PC50PC5 PC8 R281 0 P03P503
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PDF
bq24780s.pdf
TIMER 175s** 20X** ACN 1 EN_DPM 1X TYPE III IADP 7 COMPENSATION 16X/5 CHARGE_INHIBIT IDCHG 8 EAI EAO DAC_VALID EN_LEARN PWM 5X VREF_IDCHG 200mV EN_BOOST RAMP 25 BTST SRP 20 Frequency*Tj 16X TSHUT 19 155C SRN BATOVP VREF_ICHG 26 HIDRV 6mA EN_CHRG SRP-SRN 27 CHG_OCP PHASE 120mV ILIM 21 ILIM 5mV EN_REGN REGN
in „Widerstand Bestimmung“ · Mikrocontroller und Digitale Elektronik ·
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A300_ATMEGA8xxx.pdf
. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High fre- 87 2486M–AVR–12/03 quency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed
in „atMega8-16 Au beschreiben“ · Mikrocontroller und Digitale Elektronik ·
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PDF
TMS320F2812_Datasheet.pdf
Characteristics for 179-Ball GHH PARAMETER 179-GHH PACKAGE UNIT Psi 0.658 °C/W JT ΘJA 42.57 °C/W ΘJC 16.08 °C/W Table 7−2. Thermal Resistance Characteristics for 179-Ball ZHH PARAMETER 179-ZHH PACKAGE UNIT PsiJT 0.658 °C/W ΘJA 42.57 °C/W Θ 16.08 °C/W JC Table 7−3. Thermal Resistance Characteristics for 176
in „Wieder eine Elektronik-Anfängerfrage“ · Mikrocontroller und Digitale Elektronik ·
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PDF
TMC5072_datasheet.pdf
F Sinterfacee Protection 2 x current NEXTADDR & diagnostics CLK oscillator/ comparator 2 x DAC selector stallGuard2™ GNDP single wire UART SWIOP F n tro l coolStep™ SENSE RSENSE SWION F t io n co DRV2:=DRV1 Diff. Tranceivero BR2A / B Half Bridge 2 O2B2 F Step & Half Bridge 2 encoder or ENC1A/
in „TMC5072 SPI Ansteuerung“ · Mikrocontroller und Digitale Elektronik ·
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STM32_general-purpose_timer_cookbook_en.DM00236305.pdf
mode, the Vref is stocked in RAM and it is compared with the input voltage after conversion with the DAC and the analog comparator. The comparator output is internally redirected to the BRK_ACTH signal which controls the PWM state. DocID028459 Rev 2 41/73 72 Cycle-by-cycle regulation using break input
in „STM32 Timer Cookbook PWM - Beispiel 6.2“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Applnote.pdf
mode, the Vref is stocked in RAM and it is compared with the input voltage after conversion with the DAC and the analog comparator. The comparator output is internally redirected to the BRK_ACTH signal which controls the PWM state. DocID028459 Rev 1 41/73 72 Cycle-by-cycle regulation using break input
in „PWM Signalerzeugung“ · Mikrocontroller und Digitale Elektronik ·
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PDF
TMC2209_datasheet_rev1.07.pdf
pull down resistor off), ENN treated as enabled. IHOLD[1..0] selects the function of DCO: 0…2: T120, DAC, VDDH Attention: Not for user, set to 0 for normal operation! www.trinamic.com TMC2209 DATASHEET (Rev. 1.07 / 2022-JAN-18 24 G ENERAL CONFIGURATION REGISTERS (0X00…0 X0F) R/W Addr n Register Description
in „Industrielle [3D-Drucker] Bastelgrundlagen“ · Mechanik, Gehäuse, Werkzeug ·
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Datei
harware_config_default.txt
~~~~~~~~~~~~~~~~~~~ * Howard Schlunder 10/03/06 Original, copied from Compiler.h * Ken Hesky 07/01/08 Added ZG2100-specific features ********************************************************************/ #ifndef __HARDWARE_PROFILE_H #define __HARDWARE_PROFILE_H #include "GenericTypeDefs.h" #include "Compiler.h
in „I/O Pins konfigurieren“ · Mikrocontroller und Digitale Elektronik ·
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MN-RBXEB-01.pdf
memory. 06h Uncompressing the POST code next. 07h Next, initializing the CPU and the CPU data area. 08h The CMOS checksum calculation is done next. The CMOS checksum calculation is done. Initializing 0Ah the CMOS status register for date and time next. The CMOS status register is initialized.Next, 0Bh
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Datei
BASIC131-PS3.a51
into 4 4kByte Blocks to access ; peripherals consisting of two 82C55, a UPD7002 ADC and a UPD7011 DAC. ; c000h - ffffh is a 8253 Timer ; RAM from 4000h-7FFFh is battery buffered and simulate eeprom ;***************************************************************************** ;* General alterations
in „Spaß mit Kloeckner-Moeller PS3 in BASIC(?)“ · Projekte & Code ·
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PDF
ADE7953.pdf
Figure 73). ADE7953 receives a legal packet, it decodes the command as follows: The frame time is 2.08 ms. A frame-to-frame delay (t 1) of 4 ms max provides a 50% buffer on the frame time without needlessly If the number of frames obtained after the initial packet is slowing the communication. When
in „Leistungsfaktor durch Analog Device neu definiert?“ · Analoge Elektronik und Schaltungstechnik ·
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PDF
DSPIC33EP512GM710_datasheet.pdf
3 g e INTCON3 08C4 — — — — — — — — — — DAE DOOVR — — — — 0000 E 8 INTCON4 08C6 — — — — — — — — — — — — — — — SGHT 0000 P X IFS0 0800 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF
in „Probleme mit SRAM 23LCV1024“ · Mikrocontroller und Digitale Elektronik ·
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PDF
MC9S12DG128.pdf
Updated BDM clock in Figure 3-1 Removed SIM description in overview & n UPOSC spec in Table A-15 V02.02 08 Mar 08 Mar Updated electrical spec of VDD & VDDPLL (Table A-4), IOL/IOH 2002 2002 (Table A-6), C (Table A-9), C (Table A-6 & A-15), INS IN Updated interrupt pulse timing variables in Table A-6 Updated
in „HCS12 CPU Disassembler“ · Mikrocontroller und Digitale Elektronik ·
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PDF
SARA-G3-U2_SysIntegrManual__UBX-13000995_.pdf
following products: Product name Type number Firmware version SDN / IN / PCN SARA-G300 SARA-G300-00S-00 08.58 GSM.G2-TN-13007 SARA-G310 SARA-G310-00S-00 08.58 GSM.G2-TN-13007 SARA-G340 SARA-G340-00S-00 08.49 UBX-14000382 SARA-G340-01S-00 08.70 UBX-14039634 SARA-G350 SARA-G350-00S-00 08.49 GSM.G2-TN-13002 SARA-G350-01S-00 08.70 UBX-14039634 SARA-G350-01B-00 TBD TBD SARA-G350 ATEX SARA-G350-00X-00 08.49 GSM.G2-TN-13002 SARA-U260 SARA-U260-00S-00 23.20 UBX-14015739 SARA-U270 SARA-U270-00S-00 23.20 UBX-14015739 SARA-U280 SARA-U280
in „GSM-Modul (SIM908) nur analoge Ausgänge für Anruf?“ · HF, Funk und Felder ·
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PDF
db_atmega8.pdf
. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High fre- 89 2486P–AVR–02/06 quency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed
in „ADC-Input und Auswahlverfahren“ · Mikrocontroller und Digitale Elektronik ·
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PDF
datasheet__1_.pdf
Descriptor Type = Endpoint 05H 2 bEndpointAddress Endpoint Direction (1 is in) and Address = OUT8 08H 3 bmAttributes XFR Type = ISO 01H 4 wMaxPacketSize (L) Maximum Packet Size = 16 Bytes 10H 5 wMaxPacketSize (H) Maximum Packet Size - High 00H 6 bInterval Polling Interval in Milliseconds (1 for iso)
in „Emitterschaltung und LM293D“ · Mikrocontroller und Digitale Elektronik ·
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Datei
compile_Tasmota_stable_in_docker_container_versuch3.txt
ESP8266Audio/AudioOutputI2S.cpp.o Compiling .pio/build/tasmota/lib034/ESP8266Audio/AudioOutputI2SNoDAC.cpp.o Compiling .pio/build/tasmota/lib034/ESP8266Audio/AudioOutputMixer.cpp.o Compiling .pio/build/tasmota/lib034/ESP8266Audio/AudioOutputSPDIF.cpp.o Compiling .pio/build/tasmota/lib034/ESP8266Audio
in „Dlock 11827 und Tasmota - compilieren für FW-Update“ · Haus & Smart Home ·
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PDF
89C51CC01C-SLSUM.pdf
7Fh 30h 2Fh Bit-Addressable Space (Bit Addresses 0-7Fh) 20h 18h 1Fh 17h 10h 8 Registers 0Fh R0-R7 08h 00h 07h Upper 128 Bytes RAM The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect addressing mode. Expanded RAM The on-chip 1024 Bytes of expanded RAM (ERAM) are accessible
in „Bit Adressierung“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATtiny841_Datasheet.pdf
Speed Mode Frame Size Baudrate 5 6 7 8 9 10 0 – 28.8 kbps +6.67 +5.79 +5.11 +4.58 +4.14 +3.78 -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 38.4 kbps +6.63 +5.75 +5.08 +4.55 +4.12 +3.76 -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 +6.10 +5.30 +4.69 +4.20 +3.80 +3.47 57.6 kbps -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 +5.59 +4.85 +4.29 +3.85 +3.48 +3.18 76.8 kbps -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 115.2 kbps +4.57 +3.97 +3.51 +3.15 +2.86 +2.61 -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 Table 18-5. Maximum Total Baudrate Error in Double Speed Mode Frame Size Baudrate 5 6 7 8 9
in „TOCPMSA1 und TOCPMCOE Verhalten beim Attiny 841“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATtiny441_841.pdf
Speed Mode Frame Size Baudrate 5 6 7 8 9 10 0 – 28.8 kbps +6.67 +5.79 +5.11 +4.58 +4.14 +3.78 -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 38.4 kbps +6.63 +5.75 +5.08 +4.55 +4.12 +3.76 -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 +6.10 +5.30 +4.69 +4.20 +3.80 +3.47 57.6 kbps -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 +5.59 +4.85 +4.29 +3.85 +3.48 +3.18 76.8 kbps -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 115.2 kbps +4.57 +3.97 +3.51 +3.15 +2.86 +2.61 -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 Table 18-5. Maximum Total Baudrate Error in Double Speed Mode Frame Size Baudrate 5 6 7 8 9
in „Suche nach ATtiny mit ADC und Gain > 20x“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATtiny841_Datasheet.pdf
Speed Mode Frame Size Baudrate 5 6 7 8 9 10 0 – 28.8 kbps +6.67 +5.79 +5.11 +4.58 +4.14 +3.78 -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 38.4 kbps +6.63 +5.75 +5.08 +4.55 +4.12 +3.76 -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 +6.10 +5.30 +4.69 +4.20 +3.80 +3.47 57.6 kbps -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 +5.59 +4.85 +4.29 +3.85 +3.48 +3.18 76.8 kbps -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 115.2 kbps +4.57 +3.97 +3.51 +3.15 +2.86 +2.61 -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 Table 18-5. Maximum Total Baudrate Error in Double Speed Mode Frame Size Baudrate 5 6 7 8 9
in „sleep und Interrupt“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATtiny841_Datasheet.pdf
Speed Mode Frame Size Baudrate 5 6 7 8 9 10 0 – 28.8 kbps +6.67 +5.79 +5.11 +4.58 +4.14 +3.78 -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 38.4 kbps +6.63 +5.75 +5.08 +4.55 +4.12 +3.76 -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 +6.10 +5.30 +4.69 +4.20 +3.80 +3.47 57.6 kbps -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 +5.59 +4.85 +4.29 +3.85 +3.48 +3.18 76.8 kbps -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 115.2 kbps +4.57 +3.97 +3.51 +3.15 +2.86 +2.61 -5.88 -5.08 -4.48 -4.00 -3.61 -3.30 Table 18-5. Maximum Total Baudrate Error in Double Speed Mode Frame Size Baudrate 5 6 7 8 9
in „Takt-Vorskalierungsregister beim Attiny841“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ZSSC3122_cLite_Data_Sheet_rev_1_30.pdf
for Output Selections Output Selection 2 I C™ (001 B SPI (01B ) PDM_C (100 )B PDM_C+T (110 )B Pin 08 Alarm_ Low Alarm_Low Alarm_Low PDM_T Pin 09 Alarm_High Alarm_High Alarm_High Alarm_High Pin 10 Ready Ready PDM_C PDM_C Pin 12 SDA MISO SDA SDA Pin 13 SCL SCLK SCL SCL Pin 14 No input SS No input No Input
in „Hygrosens HYT221 an Atmega8 macht nichts“ · Mikrocontroller und Digitale Elektronik ·
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PDF
_Elmos__981_03.pdf
(19) VIO (31) MISO / GPIO CREC SPI host (30) MOSI / GPIO interface (29) SCK / GPI U1 (8) CREC ADC/DAC (28) SCS / GPI (11) RTXH UART host (26) RXD KInterface interface (25) TXD RTX (21) BS1 (10) RTXL (20) BS0 (32) SAVE RTXL Internal (2) RESET Logic Monitoring (1) OTEMP (9) BUSN Unit (4) AOUT Q (23) EXTAL
in „Exposed Pad anschließen? (ATSAMD20E18A-MU und ELMOS E981.03)“ · Mikrocontroller und Digitale Elektronik ·
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PDF
mega644.pdf
0x0020 - 0x005F 160 Ext I/O Reg. 0x0060 - 0x00FF 0x0100 Internal SRAM (1024/2048/4096 x 8) 0x04FF/0x08FF/0x10FF 5.3.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk cycles as described
in „AVR Controller braucht zu viel Strom“ · Mikrocontroller und Digitale Elektronik ·
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PDF
MEGA48V_88V_168V.pdf
value N/A N/A N/A N/A N/A N/A N/A N/A 14.4.5 PORTC – The port C data register Bit 7 6 5 4 3 2 1 0 0x08 (0x28) – PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC Read/write R R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 14.4.6 DDRC – The port C data direction register Bit 7 6 5 4 3 2
in „analog comparator interrupt probleme mit atmegas“ · Mikrocontroller und Digitale Elektronik ·
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PDF
AN2131_datasheet.PDF
Descriptor Type = Endpoint 05H 2 bEndpointAddress Endpoint Direction (1 is in) and Address = OUT8 08H 3 bmAttributes XFR Type = ISO 01H 4 wMaxPacketSize (L) Maximum Packet Size = 16 Bytes 10H 5 wMaxPacketSize (H) Maximum Packet Size - High 00H 6 bInterval Polling Interval in Milliseconds (1 for iso)
in „Aufrufen von Funktion legt auch vorherigen Teil des Programms lahm“ · Mikrocontroller und Digitale Elektronik ·
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PDF
AN2131_datasheet.PDF
Descriptor Type = Endpoint 05H 2 bEndpointAddress Endpoint Direction (1 is in) and Address = OUT8 08H 3 bmAttributes XFR Type = ISO 01H 4 wMaxPacketSize (L) Maximum Packet Size = 16 Bytes 10H 5 wMaxPacketSize (H) Maximum Packet Size - High 00H 6 bInterval Polling Interval in Milliseconds (1 for iso)
in „Einteilung von data, pdata, xdata, code?“ · Mikrocontroller und Digitale Elektronik ·
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Datei
TS-iP59_V05_FKA_240160A.c
P2.4| // WR1 = RD |P5.4 P2.3| // |P5.5 P2.2| // LED grün |P5.6 P6.7| frei als Spannungeingang oder DAC1 // LED rot |P5.7 P6.6| // P6.5| // P6.4| // // // Wolfgang // Januar 2018 //****************************************************************************** #include <msp430x16x.h> #include <signal.h
in „Display DEM240160A mit UC1698u einzelne Bildpunkte setzen“ · Mikrocontroller und Digitale Elektronik ·
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PDF
L6207_AN.pdf
the rest of the application) and GND. A very simple way to obtain a variable voltage without using a DAC is to low-pass filter a PWM output of a µC (see Figure 11). Assuming that the PWM output swings from 0 to 5V, the resulting voltage will be: 5V ⋅ D C ⋅ RDIV V ref = ---------------------------------
in „Schrittmotor mit L6207“ · Mikrocontroller und Digitale Elektronik ·
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PDF
en.CD00004482.pdf
the rest of the application) and GND. A very simple way to obtain a variable voltage without using a DAC is to low-pass filter a PWM output of a µC (see Figure 11). Assuming that the PWM output swings from 0 to 5V, the resulting voltage will be: 5V ⋅ D C ⋅ RDIV V ref = ---------------------------------
in „Treiberstufe fuer Faulhaber Schrittmotor“ · Mikrocontroller und Digitale Elektronik ·
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PDF
MSP430FR59xx.pdf
write Word 000Ch Section 1.16.2 06h SYSJMBC_L Read/write Byte 0Ch 07h SYSJMBC_H Read/write Byte 00h 08h SYSJMBI0 JTAG Mailbox Input 0 Read/write Word 0000h Section 1.16.3 08h SYSJMBI0_L Read/write Byte 00h 09h SYSJMBI0_H Read/write Byte 00h 0Ah SYSJMBI1 JTAG Mailbox Input 1 Read/write Word 0000h Section
in „Probleme mit Konfiguration der SPI-Schnittstelle am MSP430“ · Mikrocontroller und Digitale Elektronik ·
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PDF
MSP430FR59xx.pdf
write Word 000Ch Section 1.16.2 06h SYSJMBC_L Read/write Byte 0Ch 07h SYSJMBC_H Read/write Byte 00h 08h SYSJMBI0 JTAG Mailbox Input 0 Read/write Word 0000h Section 1.16.3 08h SYSJMBI0_L Read/write Byte 00h 09h SYSJMBI0_H Read/write Byte 00h 0Ah SYSJMBI1 JTAG Mailbox Input 1 Read/write Word 0000h Section
in „Schaltung für Vibrationsmessung mit Piezo“ · Analoge Elektronik und Schaltungstechnik ·
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PDF
3B036723d01.pdf
COCO AN7 VRH (VRH+VRL)/2 VRL 8 A/Dresultregister(ADDATA)$08 Figure 8-1 A/D converter block diagram The result of each successive comparison is stored in the SAR and, when the conversion is complete, the contents of the SAR are transferred to the read-only result data register ($08), and the conversion complete flag, COCO, is set in the A/D status/control register ($09). Warning: Any write to the A/D status/control register will abort the current conversion, reset the conversion
in „unbekanntes Touchpad, wie anschliessen und verwenden?“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATMega164_324_644_1284pa.pdf
- 0x005F 160 Ext I/O Reg. 0x0060 - 0x00FF 0x0100 Internal SRAM (1024/2048/4096/16384x 8) 0x04FF/0x08FF/0x10FF/0x40FF 8.3.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as
in „Hilfe bei AD-Wandler!“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATmega1284P_128KByte.pdf
................................................665............................. 37.4 Rev. 8272F - 08/2014....................................................665............................. 37.5 Rev. 8272E - 04/2013....................................................666.............................
in „ATmega1284P versus ohne P“ · Mikrocontroller und Digitale Elektronik ·
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PDF
tiny13_doc2535.pdf
. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized exter- nal components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the
in „Atmel AVRs: SRAM so unwichtig?“ · Mikrocontroller und Digitale Elektronik ·
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PDF
DS_AT32F421_V2.01_EN.pdf
I S interfaces is/are configured in master mode, the master clock can be output to the 2 external DAC/CODEC at 256 times the sampling frequency. Both I S can be served by the DMA controller. 2.13.3 Universal synchronous / asynchronous receiver transmitters (USART) The AT32F421 embeds two universal synchronous
in „Firmware entschlüsseln, Updateprogramm als Hilfe?“ · Softwareentwicklung ·
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PDF
tpa3244.pdf
HD Sources performance DACs such as Burr-Brown PCM52xx – Ultra Low 0.005% THD+N at 1 W into 4 Ω and DAC Family from TI (that is, PCM5242 / PCM5252). <0.01% THD+N to Clipping In addition to excellent audio performance, TPA3244 achieves both high power efficiency and very low – 60 dB PSRR (BTL, No Input
in „Class-D Verstärker TPA3244“ · Analoge Elektronik und Schaltungstechnik ·
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PDF
Keithley-2000.pdf
error EE +438 Date of calibration not set EE +439 Next date of calibration not set EE +450 100m vac dac error EE +451 1 vac dac error EE +452 10 vac dac error EE +453 100 vac dac error EE +454 100m vac zero error EE +455 100m vac full scale error EE +456 1 vac zero error EE +457 1 vac full scale error
in „Einschalt "Beep" Keithley 2000 ausschalten“ · Mechanik, Gehäuse, Werkzeug ·