Suchergebnisse für "when others"

Datei

simple_uart.vhd

shiftTx, stopTx if rising_edge(clk) then if rst = '0' then -- synchronous active-low reset TxReg <= (others => '1'); TxState <= idle; TxBusy <= '0'; one_start <= '0'; -- eventuell Datenregister einfuehren else TxBusy <= '1'; -- always busy except when explicitly not TxD <= TxReg(0); case TxState is when

in „UART Receiver oft Parity Error“ · FPGA, VHDL & Co. · 19.07.2009 16:18

Datei

IIR.vhd

); help4 <= (others => '0'); else case state is when idle => oDone <= '0'; if(iNewValue = '1') then -- If new signal arrives state <= mul; -- Change state to multiply nX(INPUT_WIDTH-1 downto 0) <= signed(iIIR_RX); --

in „IIR Filter 2. Ordnung in FPGA implementieren“ · Digitale Signalverarbeitung / DSP / Machine Learning · 26.08.2017 11:18

Datei

vga.vhd

fifo_in_full or switchpending); process(clk,reset) begin if (reset = '1') then doublebuffertreshold <= (others => '0'); clip_x_min <= (others=>'0'); clip_x_max <= (others=>'1'); clip_y_min <= (others=>'0'); clip_y_max <= (others=>'1'); elsif (clk'event and clk='1') then if (wr='1') then if addr = X"1000000"

in „SRAM auf DE2 Board“ · FPGA, VHDL & Co. · 23.08.2008 13:12

Datei

PS2_Keyboard_Ctrl.vhd

if; when WAIT_BYTE1 => Input_Buffer <= (others => '1'); -- PS/2 Startbedingung erkannt if((PS2_DataSR(1) = '0') and (PS2_ClockSR(1) = '1')) then PS2_State <= RECEIVE_BYTE1; end if; when RECEIVE_BYTE1 => -- Startbit

in „PS/2 im FPGA“ · FPGA, VHDL & Co. · 30.03.2015 09:39

Datei

BlinkLED.vhd

WHEN "1100" => asci := x"43"; --C WHEN "1101" => asci := x"44"; --D WHEN "1110" => asci := x"45"; --E WHEN "1111" => asci := x"46"; --F WHEN OTHERS => asci := x"21"; --! END CASE; return asci; end ASCII;

in „Taschenrechner in VHDL“ · FPGA, VHDL & Co. · 10.11.2012 15:42

Datei

CCD.vhd

<='0'; WHEN GETY=> IF(INIT='1')then validin<='1'; end if; Comp_Y<=BT656_DATA; IF(STATE_FLAG='1')THEN STATE<=GETCR; ELSE STATE<=GETCB; END IF; WHEN OTHERS=> LEDR(5)<='1'; END CASE; ELSE validin<='0'; STATE_FLAG<

in „Timing Requierement not met.Das System funktioniert nicht“ · FPGA, VHDL & Co. · 20.04.2015 02:45

Datei

ALU.vhd

0'; end if; when others => NULL; end case; --Pipeline Stage 3 case SelectPipe(2) is when "0000" => YPipe(2)(23 downto 16) <= (others => '0'); CarryPipe(2) <= '0'; when "0001" => YPipe(2)(23 downto 16) <= OaPipe(2)(23

in „Problem mit "Eigenbau" Pipeline ALU“ · FPGA, VHDL & Co. · 25.03.2009 05:42

Datei

lcddriver.vhd

x"A" => fifo_data <= x"41"; when x"B" => fifo_data <= x"42"; when x"C" => fifo_data <= x"43"; when x"D" => fifo_data <= x"44"; when x"E" => fifo_data <= x"45"; when x"F" => fifo_data <= x"46"; when others => fifo_data <= x"58"; --

in „LC-Display ansteuern in VHDL“ · FPGA, VHDL & Co. · 12.10.2006 12:05

Datei

Uhr.vhd

is array(1 downto 0) of ziffer; signal sekunden_neu, minuten_neu, stunden_neu : doppel_ziffer := (others => (others => '0')); signal sekunden_alt, minuten_alt : doppel_ziffer := (others => (others => '0')); signal zaehler : integer range 0 to teiler; begin -- Teilt die Taktfrequenz von 50 MHz durch 50.000.000

in „Ansteuerung LCD Anzeige Spartan“ · FPGA, VHDL & Co. · 07.02.2009 14:07

Datei

IIR_Statemachine.vhd

(others => '0'); nA1 <= (others => '0'); nA2 <= (others => '0'); nX <= (others => '0'); oDone <= '0'; oIIR_TX <= (others => '0'); else case state is when idle => oDone <= '0'; if(iNewValue = '1') then -- If

in „IIR Filter 2. Ordnung in FPGA implementieren“ · Digitale Signalverarbeitung / DSP / Machine Learning · 24.08.2017 13:15

Datei

IIR_Statemachine.vhd

(others => '0'); nA1 <= (others => '0'); nA2 <= (others => '0'); nX <= (others => '0'); oDone <= '0'; oIIR_TX <= (others => '0'); else case state is when idle => oDone <= '0'; if(iNewValue = '1') then -- If

in „IIR Filter 2. Ordnung in FPGA implementieren“ · Digitale Signalverarbeitung / DSP / Machine Learning · 25.08.2017 14:05

PDF

ALSE_UART_us.pdf

; when "111" => Divisor <= 767; -- 1.200 end if; when others => Divisor <= 7; -- n.u. end process; end case; end if; end process; -- ------------------------------ -- Rx Sampling Clock Generation -- ------

in „RS232-Empfänger mit PLD“ · FPGA, VHDL & Co. · 11.10.2006 20:27

Datei

cordic.vhd

order to support clamping d.t. an add'l offset signal sintemp, costemp : signed (16 downto 0) := (others => '0'); -- Current angle, should converge to 'phase' when iterating signal angle : signed (14 downto 0) := (others => '0'); -- Counter for our state machine (step thru all pre-defined angles (arctan

in „CORDIC in VHDL“ · FPGA, VHDL & Co. · 19.08.2014 20:12

Datei

PS2_Keyboard_Ctrl.vhd

= "10") then Input_Buffer <= PS2_DataSR(1) & Input_Buffer(10 downto 1); end if; case PS2_State is when RESET_STATE => -- Controller reseten Data_Out <= (others => '0'); Data_Ready <= '0'; Input_Buffer <= (others => '1'); if(Reset = '0') then PS2_State <= RESET_STATE; else PS2_State <= WAIT_BYTE1; end

in „PS/2 im FPGA“ · FPGA, VHDL & Co. · 27.03.2015 08:05

Datei

timer.vhd

variable_stay_cnt; -- end if; -- end process; -- process(BTN0) --WORKS -- begin -- case BTN0 is -- when '1' => -- stay_cnt <= select_cntMSECs10; -- when others => -- stay_cnt <= "1111"; -- end case; -- end process; ------------------------------------------------------------------------------- -- process

in „Ein fuer alle mal: Signal <signal> cannot be synthesized, bad synchronous description.“ · FPGA, VHDL & Co. · 09.12.2013 03:25

Datei

BlinkLED.vhd

WHEN "1100" => asci := x"43"; --C WHEN "1101" => asci := x"44"; --D WHEN "1110" => asci := x"45"; --E WHEN "1111" => asci := x"46"; --F WHEN OTHERS => asci := x"21"; --! END CASE; return asci; end ASCII;

in „Taschenrechner in VHDL“ · FPGA, VHDL & Co. · 10.11.2012 22:33

Datei

lcd_2.vhd

(4*8-1 downto 4*8-4); when others => mux_select <= "0000"; end case; end process; process(clk) variable up_limit, low_limit: integer; begin if rising_edge(clk) then if btn_rst = '1' then --Enable Signal für BCD to 7-Seg Konvertierung

in „Fehler bei Case-Anweisung“ · FPGA, VHDL & Co. · 02.04.2007 11:23

Datei

ether_tx.vhd

addr_width-1 downto 0))); process(rclk) begin if rclk'event and rclk='1' then case state_txout is when idle => data_out<=(others=>'0'); tx_en<='0'; when start=> data_out<=(others=>'0'); tx_en<='0'; when pre0=> data_out<=X"55"; tx_en<='1'; when pre1=> data_out<=X"55"; tx_en<='1'; when pre2=> data_out<

in „Ethernet GMII“ · FPGA, VHDL & Co. · 14.01.2011 19:51

Datei

vga.vhd

else InsertPixel9 := false; VGAState <= vgaIdle; HEnable <= false; VEnable <= true; HCounter <= (others => '0'); VCounter <= (others => '0'); Color <= (others => '0'); Pixel <= (others => '0'); end if; case State is when memRead => DataR <= SRAM_Data; when memASCII => NextPixel := SRAM_Data; when memColor

in „Wie aussagekräftig ist die Timinganalyse“ · FPGA, VHDL & Co. · 11.10.2006 22:32

Datei

COUNTERRegister.vhd

(7 downto 0) := (others => '0'); signal SOFT_SPEED_VALUE_sig : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); signal NULLSIG_SELECT_sig : STD_LOGIC_VECTOR(3 downto 0) := (others => '0'); signal COUNTER_RESOLUTION_sig :

in „Register in VHDL effizien implementieren?“ · FPGA, VHDL & Co. · 29.07.2009 11:51

PDF

examples.pdf

in „Bidirektionale Pins in Quartus II (Altera)“ · FPGA, VHDL & Co. · 07.12.2007 10:34

Datei

YCrCb_to_RGB.vhd

(to_unsigned(Rv,8)); ELSE R<=(others=>'1'); END IF; ENABLEOUT<=EN2; when others=> NULL; end case; end loop; for j in 0 to 3 loop case j is when 0=>Temp_CbG1<=to_integer(unsigned(Cb)-128)*11; Temp_CrG1<=to_integer(unsigned(Cr)-128)*23;

in „Timing Requierement not met.Das System funktioniert nicht“ · FPGA, VHDL & Co. · 20.04.2015 02:46

Datei

Memory.vhd

-- Markieren, dass wir das Auslesen beendet haben ASAM_en <= '0'; -- Speicher wieder deaktivieren when others => -- o In allen anderen Fällen: ... null; -- ...nichts machen end case; -- -- Daten schreiben elsif MTBus_RoutingRequest = "010" then -- Es sollen Daten geschrieben werden StateMachine := StateMachine

in „Speicherfehler im BlockRAM“ · FPGA, VHDL & Co. · 24.02.2011 19:25

Datei

aktuell_touch.txt

- state idle: wait for touch on screen -- -- ---------------------------------------------------- when idle =>CS <='1'; Data_out_tp <= '0'; ffs <= '0'; dclk_aktiv <= '0'; qdin <= 0; qdout <= 15; dinx2 <= (others => '0'); diny <= (others => '0'); if PENIRQ = '0' then if qdelay = "1111111111111111" then

in „Vmod TFT Touchscreen (von Digilent) Touch implementierung probleme“ · FPGA, VHDL & Co. · 11.12.2013 18:46

Datei

icache.vhd

0 to 511:= 0; begin if (reset_in_reset = '1') then read_state <= idle; avalon_slave_readdata <= (others => '0'); avalon_slave_waitrequest <= '0'; elsif (rising_edge(clock_in_clk)) then case read_state is when idle => if (avalon_slave_read = '1') then avalon_slave_waitrequest <= '1'; temp0 := to_integer

in „warum Registers Added for RAM Pass-Through Logic wenn kein gleichzeitiger Zugriff?“ · FPGA, VHDL & Co. · 13.06.2016 06:45

Datei

FP_Setup_Type.vhd

, x"ff80" when others; with conv_integer(SRate) select DP_SR <= 3 when 13 | 17, 4 when others; NumVal32 <= "000" & NChannels + 1 when MuxCount < 4 else "000" & SChannel + 1; BCD_Val32 <= NumVal32 + 0 when NumVal32

in „Nach type-Dekaration ganz woanders Sysntaxfehler?“ · FPGA, VHDL & Co. · 23.04.2017 18:01

Datei

SDR_CTRL.vhd

hold_time; state <= read_data after hold_time; end if; end if; case burst_size is -- burst size of 2 when "001" => wait_counter <= 5; -- burst size of 4 when "010" => wait_counter <= 4; -- burst size of 8 or no burst when others => wait_counter <= 0; end case; ------------------------ -- reading data --

in „VHDL SDRAM Controller“ · FPGA, VHDL & Co. · 24.05.2019 11:26

Datei

uart_rx.vhd

; count <= count + '1'; if state = X"0" then if rx_in_z3 = '0' and rx_in_z2 = '1' then count <= (others => '0'); state <= X"1"; else count <= (others => '0'); end if; else if count = X"8" then case state is when X"1" => if rx_in_z3 = '0' then state <= X"2"; else state <= X"0"; end if; when X"2" => rx_buffer

in „Kleiner UART / Problem“ · FPGA, VHDL & Co. · 28.02.2007 00:17

Datei

EthernetTXWrapped.vhd

; protocol <= ethTXProtocol; counter <= x"0000"; end if; when stPushLength => case counter(0) is when '0' => fifoIn <= frameLength(15 downto 8); counter(0) <= '1'; when '1' => fifoIn <= frameLength(7 downto 0); counter(0) <= '0'; state <= stPushHeader; when others

in „100MBit Ethernet mit Spartan 3E Starter Kit“ · FPGA, VHDL & Co. · 06.02.2011 00:57

Datei

EthernetTXWrapped.vhd

; protocol <= ethTXProtocol; counter <= x"0000"; end if; when stPushLength => case counter(0) is when '0' => fifoIn <= frameLength(15 downto 8); counter(0) <= '1'; when '1' => fifoIn <= frameLength(7 downto 0); counter(0) <= '0'; state <= stPushHeader; when others

in „100MBit Ethernet mit Spartan 3E Starter Kit“ · FPGA, VHDL & Co. · 21.02.2011 15:57

Datei

main_src.vhd

machine für folgende 3 Statuse auf 0 gesetzt werden with AKT_STATUS select TRANSPORT_INIT <= '0' when INIT | FERTIG, '1' when others; --multiplexer richtig schalten with AKT_STATUS select SCHALT <= '1' when INIT, '0' when others; --befindet sich die main s. m. in der Init phase so muss das bit auf 1 gesetzt werden --um die Init s. m. zu triggern with AKT_STATUS select INIT_START <= '1' when INIT, '0' when others; --gibt Aufschluss darüber, ob Daten oder Befehle übertragen werden --RS=0 für Befehle und RS=1 für Daten with AKT_STATUS select LCD_RS <= '0' when SET_ADDR | INIT, '1' when others

in „FF/Latch Warnung bei LCD Display“ · FPGA, VHDL & Co. · 15.02.2012 15:28

Datei

test_function_mcfor.vhd

<= run; when "00000100" => next_state <= reverse; when "00000010" => next_state <= count; when "-------1" => next_state <= hold; when others => next_state <= btnError; end case; end process input_pr; sync_pr : process

in „Delay zur Realisierung von LED-Blinken /mit XILINX - Spartan2E“ · FPGA, VHDL & Co. · 17.03.2009 10:40

Datei

main_src.vhd

machine für folgende 3 Statuse auf 0 gesetzt werden with AKT_STATUS select TRANSPORT_INIT <= '0' when INIT | PAUSE | FERTIG, '1' when others; --multiplexer richtig schalten with AKT_STATUS select SCHALT <= '1' when INIT, '0' when others; --befindet sich die main s. m. in der Init phase so muss das bit

in „FF/Latch Warnung bei LCD Display“ · FPGA, VHDL & Co. · 13.02.2012 11:59

Datei

spi_struct.h

state.*/ uint32_t reserved24 : 5; /*reserved*/ uint32_t ck_idle_edge : 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.*/ uint32_t cs_keep_active : 1; /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/ uint32_t quad_din_pin_swap

in „C > Struct > Pointer - Adresszuweisung“ · Mikrocontroller und Digitale Elektronik · 10.11.2024 11:50

Datei

AC1_2011.vhd

PIO PIOM1 <= M1 and Reset ; -- Verknüpfung -- Signal IO1x erzeugen IO1x <= IORQ when ADR(7 downto 3) = "00010" and WR = '0' else '1' ; -- Modul 1 Latch auf IO-PORT 14H IO14(3 downto 0) <= (others => '0') when (Reset = '0') else DB(3 downto 0) -- Latch laden when (IO1x = '0' and ADR(2 downto 0)="100") else IO14(3 downto 0) ; -- Modul 3 Latch auf IO-PORT 15H IO15 <= (others => '0') when (Reset = '0') else DB -- Latch laden when (ADR(7 downto 0) = x"15" AND IORQ = '0' AND WR = '0') else IO15 ; -- Modul 1 IO16H Register.. RAM ab 0..FFFH IO16 <= '0' when (Reset = '0') else

in „Fitterproblem“ · FPGA, VHDL & Co. · 26.01.2011 23:28

Datei

FP_Setup_Type.vhd

, x"ff80" when others; with to_integer(unsigned(SRate)) select DP_SR <= 3 when 13 | 17, 4 when others; NumVal32 <= "000" & std_logic_vector(unsigned(NChannels) + 1) when unsigned(MuxCount) < 4 else "000" & std_logic_vector

in „Nach type-Dekaration ganz woanders Sysntaxfehler?“ · FPGA, VHDL & Co. · 24.04.2017 12:55

Datei

TSBUF.vhd

schnipsel OF blafasel IS SIGNAL OUT_EN : BIT := '0'; SIGNAL OUT_DATA : STD_LOGIC_VECTOR( 7 DOWNTO 0) := (OTHERS => '0'); SIGNAL IN_DATA : STD_LOGIC_VECTOR( 7 DOWNTO 0) := (OTHERS => '0'); SIGNAL CFG_DATA : STD_LOGIC_VECTOR( 7 DOWNTO 0) := (OTHERS => '0'); SIGNAL X_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS

in „VHDL-Tristatebuffer will nicht“ · FPGA, VHDL & Co. · 12.10.2006 05:57

Datei

74185.vhd

1' WHEN 28, -- '0' WHEN OTHERS; -- WITH conv_input SELECT -- bcd_o(3) <= -- '1' WHEN 4, '1' WHEN 9, '1' WHEN 14, '1' WHEN 19, -- '1' WHEN 24, '1' WHEN 29, -- '0' WHEN OTHERS; -- WITH conv_input SELECT -- bcd_o

in „VHDL Design für den IC 74185“ · FPGA, VHDL & Co. · 03.12.2006 20:02

Datei

MultiplierNEU.vhd

signal SUM1,SUM2,SUM3 : bit_vector ( 8 downto 0 ); begin PP1: process (A,B,H) begin case B(0) is when '1' => H(0)<=A(0); H(1)<=A(1); H(2)<=A(2); H(3)<=A(3); when others => H <=(others=>'0'); end case; end process PP1; PP2: process(A,B,I) begin case B(1) is when '1' => => I(0) <= '0'; => I(1) <=A(0);

in „Case-When Fehlermeldung brauche Hilfe“ · FPGA, VHDL & Co. · 21.11.2009 15:36

Datei

npl30d.vhd

and (P26 = '0')) then mmc_ireg <= '0'; elsif PLCLK1 = '1' and PLCLK1'event then case state is when state_wait_start => mmc_coreg <= '0'; mmc_doreg <= '0'; mmc_creg <= (others=>'0'); mmc_out <= mmc_mosi_reg; if (start = '1') then state <= state_clock_low; end if; when state_clock_low => mmc_coreg

in „Probleme bei der Umstellung von Verilog nach VHDL“ · FPGA, VHDL & Co. · 26.10.2009 23:16

Datei

i2c_slave.vhd

read_process: process(clock, reset) begin if reset = '1' then read_state <= idle; input_shift <= (others => '0'); else if rising_edge(clock) then case read_state is when idle => if read_byte then input_shift_count <= 7; read_state <= read_bit; end if; if read_ack then input_shift_count <= 0; read_state

in „i2c slave zum testen“ · FPGA, VHDL & Co. · 06.04.2009 08:41

Datei

SECU.vhd

; when WaitBussyWait => FSMState <= WaitBussy; when NOP => BusAdress <= (Others => '0'); BusConf <= (Others => '0'); BusFlags <= (Others => '0'); BusDataDirekt <= (Others => '0'); NOPCounter <= NOPCounter

in „Problem mit dem Laden eines Counters“ · FPGA, VHDL & Co. · 21.05.2009 00:30

Datei

mt48lc32m8a2.vhd

" Bank-3 "; WHEN others => ASSERT false REPORT InstancePath & partID & ": Could not decode bank" & " selection - results may be incorrect." SEVERITY SeverityMode; END CASE; END IF; -- The Big State Machine IF (rising_edge

in „Problem mit vital.timing und vital.primitives“ · FPGA, VHDL & Co. · 26.10.2025 21:27

Datei

idct.vhd

process idct_read_p; data_p: process(clk,reset) --(1 clk) begin if(reset='1') then data_a_reg(0)<=(others => '0'); data_a_reg(1)<=(others => '0'); data_a_reg(2)<=(others => '0'); data_a_reg(3)<=(others => '0'); data_a_reg(4)<=(others => '0'); data_a_reg(5)<=(others => '0'); data_a_reg(6)<=(others => '0

in „Simulationsproblem bei XOR-Verknüpfung“ · FPGA, VHDL & Co. · 12.10.2006 12:06

Datei

74185.vhd

1' WHEN 28, -- '0' WHEN OTHERS; -- WITH conv_input SELECT -- bcd_o(3) <= -- '1' WHEN 4, '1' WHEN 9, '1' WHEN 14, '1' WHEN 19, -- '1' WHEN 24, '1' WHEN 29, -- '0' WHEN OTHERS; -- WITH conv_input SELECT -- bcd_o

in „VHDL Design für den IC 74185“ · FPGA, VHDL & Co. · 01.12.2006 07:17

Datei

TSBUF.vhd

RD Signal ... ... signal OUT_EN : bit:='0'; signal OUT_DATA : STD_ULOGIC_VECTOR(7 downto 0) := (others => '0'); signal IN_DATA : STD_ULOGIC_VECTOR(7 downto 0) := (others => '0'); signal CFG_DATA : STD_ULOGIC_VECTOR(7 downto 0) := (others => '0'); signal X_DATA : STD_ULOGIC_VECTOR(11 downto 0) := (others

in „VHDL-Tristatebuffer will nicht“ · FPGA, VHDL & Co. · 12.10.2006 05:57

Datei

Speed.vhd

<= INIT; when V1 => IMP4 <= '1'; --DIR <= '1'; F_ZUSTAND <= V10; when V2 => IMP4 <= '1'; --DIR <= '1'; F_ZUSTAND <= V20; when V3 => IMP4 <= '1'; --DIR <= '1'; F_ZUSTAND <= V30; when V4 => IMP4 <= '1'; --DIR <= '1

in „[VHDL] Komponenten Einbinden und wegoptimieren von Signalen verhindern“ · FPGA, VHDL & Co. · 08.06.2011 16:43

Datei

idt70V3319.vhd

TAP_state = Select_DR_Scan THEN BSR_READ <= false; ELSIF TAP_state = Shift_DR THEN CASE instruction IS WHEN idcode => TDO_zd := IDreg(0); WHEN bypass => TDO_zd := bpr; WHEN extest => TDO_zd := bsr(0); WHEN sample_preload => TDO_zd := bsr(0); WHEN others => null; END CASE; ELSIF TAP_state = Exit1_DR THEN TDO_zd

in „Fehler bei RAM-Simulation“ · FPGA, VHDL & Co. · 14.02.2008 10:37

Datei

TEM_uni_5_adc_stream.vhd

ADC_data_ready <= AD7356_56_data_ready; when others => ADC_data <= fifo_counter; ADC_data_ready <= fifo_counter_ready; end case; --ADC_data <= fifo_counter; ADC_data_ready <= fifo_counter_ready; end process; --------- write to FIFO -----------

in „Wie Clockdomain crossing für FT232H, wie debuggen?“ · FPGA, VHDL & Co. · 26.04.2017 17:39

Datei

Signed_Multiplier.vhd

Mult_state; begin process begin wait until rising_edge(clk); if(reset='1') then intOperant_A <= (others => '0'); intOperant_B <= (others => '0'); accu <= (others => '0'); bitCounter <= 0; intbusy <= '0'; Mult_state_reg <= reset_state; else case Mult_state_reg is when reset_state => accu <= (others =>

in „Ressourcen optimieren für signed multiplier“ · FPGA, VHDL & Co. · 15.11.2020 11:56

Suchergebnisse für "when others"

2977 Treffer für when others Suchergebnisse für "when others"

2977 Treffer für when others