Suchergebnisse für "when others"

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3880 Treffer für when others Suchergebnisse für "when others"

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  • Thread

    Prozess mit kombinatorischer und getakteter Logik

    next_state <= state; -- Default-Werte shifter_cnt <= 0; case state is when sReset=> next_state <= sState1; when sState1=> -- Hier wird noch irgendwas mit shifter_data berechnet -- Eigentlich wird aus shifter_data auch shifter_cnt

    Default-Zustände für Cases in denen Werte nicht beschrieben werden lut_addr <= '0'; lut_addr <= (others => '-'); case state is when sReset=> state <= sTableLookup; when sTableLookup=> -- Daten aus Stream nehmen um Tabelle zu indizieren (table lookup)

    FPGA, VHDL & Co. ·Marius S. · ·16 Antworten

  • Thread

    Wie einen Counter mit JK flipflops in VHDL beschreiben?

    end Counter; architecture arc of Counter is signal cnt : unsigned (3 downto 0) := (others=>'0'); begin cnt <= cnt+1 when rising_edge(clk); q <= std_logic_vector(cnt); end architecture arc ; [/vhdl] Hier noch ein paar Lösungen auf die Fragen, die Markus F. schrieb im Beitrag

    Lothar M. schrieb im Beitrag #6199329: > begin > > q <= cnt+1 when rising_edge(clk); > > q <= std_logic_vector(cnt); > > end architecture arc ; Das sollte doch bestimmt so aussehen: cnt <= cnt+1 when rising_edge(clk); q <= std_logic_vector(

    FPGA, VHDL & Co. ·Patrick M. · ·16 Antworten

  • Datei

    ITPModul_tb.vhd

    Koordinate Z signal tb_XT : std_logic_vector(31 downto 0) := (others => '1'); -- Koordinate X relativ (XE-XS) signal tb_YT : std_logic_vector(31 downto 0) := (others => '1'); -- Koordinate Y relativ (YE-YS) signal tb_ZT : std_logic_vector(31 downto 0) := (others =>

    in „Post-Map simulation mit ModelSim“ · FPGA, VHDL & Co. ·

  • Datei

    Fifo.vhd

    unsigned (Addrbreite-1 downto 0) := (others => '0'); signal rdcnt : unsigned (Addrbreite-1 downto 0) := (others => '0'); type speicher is array(0 to (2**Addrbreite)-1) of unsigned(Wortbreite-1 downto 0); signal memory : speicher; signal full_loc

    in „Frage zu fifo“ · FPGA, VHDL & Co. ·

  • Datei

    exmple.vhd

    CLK) begin if CLK'event and CLK = '1' then if Koeffi_WR = '1' and WR = '0' then case Koeffi_Adr is when b"000" => Koeffi_0 <= Koeffi_in; when b"001" => Koeffi_1 <= Koeffi_in; when b"010" => Koeffi_2 <= Koeffi_in; when others => null; end case; WR <= '1'; elsif Koeffi_WR = '0' then WR <= '0'; end if; end

    in „Regelkreis“ · FPGA, VHDL & Co. ·

  • Thread

    Wie Takt in VHDL umschalten?

    signal MUX : bit_vector(1 downto 0); signal ENABLE : bit; MUX <= TASTE & RUN; case MUX is when "01" => ENABLE <= CLK_1HZ; when "10" => ENABLE <= CLK_128HZ; when others => ENABLE <= "0"; end case; process (SysCLK) begin if (SysCLK = '1' and SysCLK'event) then if (TASTE =

    FPGA, VHDL & Co. ·Sebastian · ·11 Antworten

  • Thread

    Frage zum Warning Latch

    BRAM_WRITE_OR_READ_ENABLE, FLASH_ENABLE); with SWITCH select WEITERGABE_DATEN_BRAM<= BRAM_OUT_DATA_2 when "01", BRAM_OUT_DATA_1 when "11", WEITERGABE_DATEN_BRAM when others; [/vhdl] Jetzt kommt die Warnung Latch gefunden... und im Prinzip

    FPGA, VHDL & Co. ·Igor · ·5 Antworten

  • Datei

    la.vhd

    )) (95 downto 64); when "10" => BBUS_out.BRDATA<=fifo(to_integer(unsigned( BBUS_IN.BADDR(13 downto 4)) +trigger_pos)) (63 downto 32); when "11" => BBUS_out.BRDATA<=fifo(to_integer(unsigned( BBUS_IN.BADDR(13 downto 4)) +trigger_pos)) (31 downto 0); when others =>NULL; END CASE; end if; end process; BBUS_out.BREADYOUT <= '1'; end Behavioral;

    in „Alternative zu ChipScope“ · FPGA, VHDL & Co. ·

  • Datei

    uart.vhd

    ; end if; when TX_STATE_TRANSMIT => if ce_tx = '1' then if tx_bit_cnt = WIDTH+1 then tx_state <= TX_STATE_IDLE; tx_busy <= '0'; else tx <= tx_data(tx_bit_cnt); tx_bit_cnt <= tx_bit_cnt + 1; end if; end if; end case

    in „[Anfänger] RS232 Modul in VHDL - Kritik erwünscht“ · FPGA, VHDL & Co. ·

  • Thread

    maximale Xilinx CPLD clock Frequenz

    ändern.Dann kannst du sowas benutzen. [vhdl] with readvect select count <= t_cnt_tmp(7 downto 0) when "100" , count <= t_cnt_tmp(15 downto 8) when "010" , count <= t_cnt_tmp(23 downto 16) when "001" , count <= (0 to 7 => 'Z') when others , [/vhdl] Ach und nochwas benutze keine VHDL

    FPGA, VHDL & Co. ·Reinhard J. · ·22 Antworten

  • Thread

    Gibt es Steckbretter für größere Drahtdurchmesser?

    out to be) and then credits are subtracted from your account when you utilize a service or function. The present and delivery are all billed separately. The presents or flower supply will make your lady feel special. Live chat. It is possible for you to to talk with

    ladies they need to speak to. Ladies that use on-line dating websites will not neglect them even when they are extremely busy. The process entails visiting your electronic mail inbox for a message which will likely be offered as a link. One greeting message is enough. Sometimes, a simple “heyâ€

    Analoge Elektronik und Schaltungstechnik ·Thomas · ·22 Antworten

  • Thread

    extrem kurzen Impuls erzeugen und nutzen

    Zählerstufen. Fertig ist der Lack. [vhdl] Signal Counter, Counter_2 : unsigned(3 downto 0) := (others => '0'); Signal Reset : std_logic := '0'; Process(CLK) Begin if rising_edge(CLK)then if Reset = '1' then Counter <= (others => '0'); else Counter <= Counter + 1; end if; end if; end Process; Reset <= '1' when Counter = 9 else '0'; Process(CLK) Begin if rising_edge(CLK)then if Reset = '1' then Counter_2 <= Counter_2 + 1; end if; end if; end Process; [/vhdl] Mal schnell 2 kaskadierte

    FPGA, VHDL & Co. ·Ralph H. · ·10 Antworten

  • Thread

    SPI im CPLD mit State Machine - geht das so?

    (7 downto 0); begin process (CLK, Reset) is begin if Reset = '1' then SPI_Reg <= (others => '0'); MISO <= '0'; Zustand <= SPI_Idle; elsif rising_edge (CLK) then case Zustand is when SPI_Idle => if SS = '0' then MISO <= SPI_Reg (7); Zustand <= SPI_waitSckH; end if; when SPI_waitSckH => if SCK = '1' then SPI_Reg <= SPI_Reg (6 downto 0) & MOSI; Zustand <= SPI_waitSckL; end if; when SPI_waitSckL

    FPGA, VHDL & Co. ·Erwin Endres · ·12 Antworten

  • Thread

    Schleifen in Zustandsmaschinen die Zweite

    sollte keine Rolle spielen. Also wo ist der "Denk"-Fehler ? [vhdl] case load_key_state is when zero => -- Vorgang nicht abgeschlossen done <= '0'; -- Schreiberlaubnis erteilen write_enable_key <= '1'; -- Adresse und Daten zuweisen address_key <= (others => '0');

    abgeschlossen done <= '1'; -- Ende load_key_state <= two; end if; when two => null; end case; [/vhdl]

    FPGA, VHDL & Co. ·Hans-Werner · ·7 Antworten

  • Thread

    Wie Clockdomain crossing für FT232H, wie debuggen?

    ; ADC_data_ready <= AD7356_34_data_ready; when "100" => ADC_data <= AD7356_4_data; ADC_data_ready <= AD7356_34_data_ready; when "101" => ADC_data <= AD7356_5_data; ADC_data_ready <= AD7356_56_data_ready; when "110" => ADC_data <= AD7356_6_data; ADC_data_ready <= AD7356_56_data_ready; when others => ADC_data <= fifo_counter; ADC_data_ready <= fifo_counter_ready; end case;[/vhdl] Wenn ich das feste auf den Zähler als Datengenerator verbinde [vhdl] ADC_data <= fifo_counter; ADC_data_ready

    FPGA, VHDL & Co. ·Gustl B. · ·2 Antworten

  • Thread

    viele std_logic_vector vergleichen - minimum finden

    Pseudocode !! Vergleich <= (Var1 < Var2) & (Var3 < Var4); case vergleich is when "00" => Result <= Var2 < Var4; when "01" => Result <= Var2 < Var3; when "10" => Result <= Var1 < Var4; when others => Result <= Var1 < Var3; end case Gruß Hagen

    FPGA, VHDL & Co. ·Sssssss · ·4 Antworten

  • Datei

    drehgeber.vhd

    := '0'; begin wait until rising_edge(CLK_50MHZ); cu := '0'; -- lokale Werte cd := '0'; case z is when Z00 => if (e = "01") then z <= Z01; cu := '1'; elsif (e = "10") then z <= Z10; cd := '1'; end if; when Z01 => if (e = "11") then z <= Z11; cu := '1'; elsif (e = "00") then z <= Z00; cd := '1'; end if; when Z11 => if (e = "10") then z <= Z10; cu := '1'; elsif (e = "01") then z <= Z01; cd := '1'; end if; when Z10 => if (e = "00") then z <= Z00; cu := '1'; elsif (e = "11") then z <= Z11; cd := '1'; end if

    in „Signal von Drehgeber nicht erkannt“ · FPGA, VHDL & Co. ·

  • Datei

    Segmentanzeige.vhd

    SegmentVector0 : std_logic_vector (6 downto 0):= "0000000"; begin if Rst = '1' then AllSegments := (Others => '1'); SegmentVector0 := (Others => '0'); elsif rising_edge(En) then ASCIICheckSegment(Ergebnis,SegmentVector0); AllSegments := SegmentVector0 & AllSegments(27 downto 7); end if; end process; Segmente

    in „RS232 Daten Empfangen, Vergleichen, auf Monitor ausgeben (SPARTAN 3)“ · FPGA, VHDL & Co. ·

  • PDF

    ATxmega_schematic.pdf

    for very low power consumption, and thus when selecting crystals, see Table 4-3 for maximum ESR recommendations on 9 pF and 12.5 pF crystals. The Low-frequency Crystal Oscillator provides an internal load capacitance of typical 8.0 pF. Crystals

    in „Stromversorgung XMega“ · Mikrocontroller und Digitale Elektronik ·

  • Thread

    VHDL 1993: Wie maximalwert eines Integer ranges aus Signal bestimmen

    subtype int5_t is integer range 0 to 31; Und dann signal sig : int5_t; is_max <= '1' when sig = int5_t'high else '0'; Dann ist is_max 1 wenn sig den Wert 31 hat.

    Diesbezueglich habe ich in der Vgh keinen anderen Weg gesehen, als explizites Ausrollen mit case/when/others.

    FPGA, VHDL & Co. ·M. N. · ·7 Antworten

  • Thread

    Zugriff über Testpattern auf Konstanten einer Library

    nochmals eintippen und vor allem parallel zur Library warten. Z.B.: [vhdl] case tp_string is when "ADDR_SET_MINTIME" => tp_addr := ADDR_SET_MINTIME; when "ADDR_SET_MAXTIME" => tp_addr := ADDR_SET_MAXTIME; ... when others => tp_addr := x"0000"; end case; [/vhdl]

    FPGA, VHDL & Co. ·Matthias G. · ·5 Antworten

  • Thread

    Kein Gigabit Lan trotz richtiger einstellungen

    . When I switched off the capability "Energy-efficient Ethernet" my modem could make a gigabit connection with my laptop without problems. Warning. On an other computer I got a blown ethernet port! Possibly

    computer I got a blown ethernet port! Possibly by using the > Windows Problem solver too often, when a mismatch occurred. > My gigabit modem/router has an unusual high power supply of 27Watts..., > most have 18 Watts. Best part. Thx

    PC Hard- und Software ·Steven Mailer · ·70 Antworten

  • Thread

    CPLD in-Clock Problem

    Test; architecture Behavioral of Test is signal counter : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0'); begin process ( GCLK ) begin if rising_edge ( GCLK ) then counter <= counter + 1; end if; end process ; LED <= counter; end Behavioral;[/vhdl] Simuliert

    es mal so, dass du einfach einen Tastereingang auf ein paar LEDs ausgibst: [vhdl] led <= "0101" when taster = '1' else "1010"; [/vhdl] Dann siehst du schon mal, ob ein Eingang überhaupt das tut was du willst. Und dann nimm einen /vernünfitgen und stabilen/ Takt und probier das nochmal mit dem

    FPGA, VHDL & Co. ·phanaton · ·25 Antworten

  • Datei

    EthernetTX.vhd

    '0'; nextState <= stSendPayloadLowNybble; when others => end case; else nextState <= stSendHeader; if counter(4 downto 0) >= '1' & x"9" then -- when the tx_clk is high, use the time to latch tx data nextTxData <= txData2; nextTxData2 <= txData3;

    in „100MBit Ethernet mit Spartan 3E Starter Kit“ · FPGA, VHDL & Co. ·

  • Thread

    Sequenz ausgeben

    = "001"; : process begin wait until rising_edge(clk); case state is when "001" => state <= "010"; when "010" => state <= "100"; when others => state <= "001"; end case; end process; leds <= state; [/vhdl] 2) Du kannst einen Zähler

    FPGA, VHDL & Co. ·Zappelphilipp · ·15 Antworten

  • Datei

    CosFP.vhd

    RANGE 0 TO 7:= 0; BEGIN IF rising_edge(clk) THEN IF nrst = '0' THEN state := 0; cntrclk := 0; --(OTHERS => '0'); ELSE CASE state IS WHEN 0 => IF cecos = '1' THEN ce1 <= '1';-- start für 1-x, x`2, ComP0.5 state := 1; ELSE state := 0; END IF; WHEN 1 => --- Ausführen ain :=ainp^2 ce1 <= '0'; ce2 <= '1';-- start für fkt_c cntrclk := 11; state := 2; WHEN 2 => ---- mul2mX,2powX fertig IF cntrclk = 0 THEN state := 0;--warten auf nächste Start ELSE ce2 <= '0'; cntrclk := cntrclk -1; state := 2; END IF; WHEN OTHERS => state := 0; END CASE; END IF; -- if

    in „Post-Map simulation mit ModelSim“ · FPGA, VHDL & Co. ·

  • Thread

    Anfängerversuch "Shifter"

    einen Shifter realisieren, aber so ganz funktioniert es noch nicht. [vhdl] case exp is when "000000" => full_range_real_out(13 downto 0) <= real_in(13 downto 0); when "110010" => -- links shift um 14 full_range_real_out(27 downto 14) <= real_in(13 downto 0); ....[/vhdl

    Bits von full_range_real_out auch zuweist. Am Besten per default: [vhdl] full_range_real_out <= (others => '0'); case exp is when "000000" => full_range_real_out(13 downto 0) <= real_in(13 downto 0); when "110010" => -- links shift um 14 full_range_real_out(27 downto 14

    FPGA, VHDL & Co. ·Der Lars · ·2 Antworten

  • Datei

    atari_tb.vhd

    Refreshausgang, um eigene Zugriffe auf den Bus zu ermöglichen (über BC847 Transistor) begin tb_data <= ( others => 'Z'); tb_ram_rom_adr <= ( others => 'Z'); tb_rdy <= '0'; tb_switch_in <= '0'; tb_phi2 <= not tb_phi2 after tb_phi2_period / 2 when simulation_run; tb_reset_n_in <= '0', '1' after 10 * tb_phi2_period; tb_clk50 <= not tb_clk50 after tb_clk50_period / 2 when simulation_run; tb_gpio <= ( others => 'Z'); tb_gpin <= "00"; process begin wait until rising_edge( tb_phi2); tb_phi2short <= '1'; wait for tb_phi2_period * 1 / 3; tb_phi2short <= '0'; if not simulation_run

    in „Altera CycloneI ATARI-FPGA“ · FPGA, VHDL & Co. ·

  • Thread

    Bitsampling mit VHDL-AMS

    i in 1 to 8 loop case bitstream_in is -- momentanen Wert des Bitstream beachten when ‘0’ => counter0 := counter0 + 1; when ‘1’ => counter1 := counter1 + 1; end case; end loop; -- Mehrheitsentscheidung if counter0 > counter1 then bitstream_sampled <=

    i in 1 to 8 loop case bitstream_in is -- momentanen Wert des Bitstream beachten when ‘0’ => counter0 := counter0 + 1; when ‘1’ => counter1 := counter1 + 1; end case; end loop; [/vhdl] hier fragst du doch 8 mal hintereinander den gleichen Wert ab. Du darfst

    FPGA, VHDL & Co. ·Sunny · ·11 Antworten

  • Thread

    FSM als pipeline Ausführung?

    passenden Stellen eingefügt: [vhdl] y1 <= (b1 * b2) + (datain - a1 - b2) * a1; y2 <= y1 when rsing_edge(clk); y <= y2 when rsing_edge(clk); [/vhdl] Allerdings ist das dann kein Pipelining, sonden einfach das Einfügen von zusätzliche Latency-Takten.

    Ph_tmp <= '0'; end if; cnt <= cnt + 1; when others => --count up if cnt = 1 then cntDwn <= '0'; TQ14_tmp <= to_integer(unsigned( TQ14(cntWidth-1 downto 0) ));--update compare wert bei count = 0 end if;

    FPGA, VHDL & Co. ·Linus · ·29 Antworten

  • Datei

    SerialMultiplier.vhd

    ) := (others => '0'); signal lowProductShiftReg : unsigned(multiplicator'range) := (others => '0'); signal processingShiftReg : unsigned(multiplicator'high + 2 downto 0) := (others => '0'); signal lastNewData :

    in „Signal auf bestimte Range von Port mappen“ · FPGA, VHDL & Co. ·

  • Datei

    sixcounter.vhd

    debounce_type is array(0 to 5) of std_logic_vector(2 downto 0); signal debsr : debounce_type := (others=>(others=>'0')); -- 6 Stück 32 Bit Zähler als Array definieren type counter_type is array(0 to 5) of unsigned(31 downto 0); signal cnt : counter_type := (others=>(others=>'0')); -- der Schattenspeicher

    in „Mehrkanal Impulszähler PIC“ · Mikrocontroller und Digitale Elektronik ·

  • Thread

    "This signal is connected to multiple drivers"

    Zeit für Selbstgespräche: Was mir einfällt ist [vhdl] S <= not S1 when V = '0' else S2; P: process(S) begin if rising_edge(S) then if V = '0' then Q <= ... else Q <= ... end if; end if; end process; [/vhdl] Ist das "die" Lösung

    [/vhdl] Das wissen wir ja nicht, ob es so gemeint ist. Vielleicht eher so? [vhdl] ... Q <= Q1 when V = '0' else Q2; [/vhdl] Sieht mir nämlich eher danach aus, als ob V darüber entscheidet, wie sich Q verhält. 'or' wäre dann genauso falsch wie 'and' oder 'xor'.

    FPGA, VHDL & Co. ·vhtl · ·12 Antworten

  • Thread

    Problem bei Synthese

    Hello wieder! ich muss erstmal das program stück posten! when S2 => --Zustand S2 if counter<15 then counter<=counter+1; Folge_z<=S3;

    Folge_z<=S0; counter<=(others=>'0'); --Data<=(others=>'0'); end if; Das problem bei mir wenn ich den zustand S2 erreiche wird counter inkrementiert und wenn ich es wieder verlasse

    FPGA, VHDL & Co. ·Gast_1 · ·5 Antworten

  • Thread

    IIR Filter 2. Ordnung in FPGA implementieren

    Wortbreite. > > So breit rechnest Du nicht?! [vhdl] signal nB0 : signed(83 downto 0) := (others => '0'); -- 64 + 4 Guard + 16 Bit signal nB1 : signed(83 downto 0) := (others => '0'); -- 64 + 4 Guard + 16 Bit signal nB2 : signed(83 downto 0) := (others => '0'); -- 64 + 4 Guard + 16 Bit signal nA1 : signed(84 downto 0) := (others => '0'); -- 64 + 4 Guard + 17 Bit signal nA2 : signed(83 downto 0) := (others => '0'); -- 64 + 4 Guard + 16 Bit[/vhdl] Sind doch 85/84 Bit für die Multiplikationen. Die Addierer können ja

    Digitale Signalverarbeitung / DSP / Machine Learning ·Marcel D. · ·100 Antworten

  • Thread

    RGMII mit Cyclone IV + Probleme mit SignalTrap

    , frame_counter, start_tx, error_tx) begin if start_tx = '1' then case tx_clk is when '0' => tx_data <= framedata_neu (to_integer(frame_counter)*8 + 3 downto (to_integer(frame_counter)*8)); when '1' => tx_en <= '1'; tx_data <= framedata_neu (to_integer(frame_counter)*8 + 7 downto (to_integer(frame_counter)*8+4)); when others => end case; else if tx_clk = '1' then tx_en <= '0'; end if; end if; end process; [/vhdl] Die Startbedingung und Abbruchbedingung wird von einer FSM aus einem

    FPGA, VHDL & Co. ·nuts · ·3 Antworten

  • Thread

    Kombinatorische Signale über mehrere Entities routen nicht möglich?

    Synthese das automatisch, wenn ich etwas schreibe wie [VHDL] if A_OE = '0' then Data_out <= (others=>'Z'); end if; [/VHDL]

    FPGADataOut when A_OE = '0' else (others=>'Z'); FPGADataIn <= Datenbus_uC; [/vhdl]

    FPGA, VHDL & Co. ·Steffen Hausinger · ·13 Antworten

  • Thread

    Motorola Vip19x0 (Big brother of Vip1710)

    tool too. I use windows version but I have to use switch with mirrored port and repeatly boot STB. When I try it only with pc I have no luck. When I disconnect STB multicast stop. There was some live check or heartbeat from STB. Maybe it helps you.

    Thnx. I'll make an IIP out of it when I've got the time.

    Mikrocontroller und Digitale Elektronik ·Martin V. · ·306 Antworten

  • Thread

    Verhalten von Signalen nach zuweisung

    = EINS; else addier_zustand <= IDLE; end if; when EINS => sax1_eingang_schreiben <= '0'; sax1_rdy_in <= '1'; if (fertig_geschrieben = '1') then addier_zustand <= IDLE; fertig_gerechnet <= '0';

    fertig_gerechnet <= '1'; end if; end if; when others => addier_zustand <= IDLE; end case; end if; end if; end process ADDIERE_PROCESS; [/pre]

    FPGA, VHDL & Co. ·Der Anfänger · ·7 Antworten

  • Datei

    uart.vhd

    <= clk_count_tx + 1; ce_tx <= '0'; else clk_count_tx <= 0; ce_tx <= '1'; end if; case tx_state is when TX_STATE_IDLE => -- Reset data tx_bit_cnt <= 0; clk_count_tx <= 0; tx_data <= '1' & din; if tx_start = '1' then tx_busy <= '1'; -- Write start bit tx <= '0'; tx_state <= TX_STATE_TRANSMIT; end if; when

    in „[Anfänger] RS232 Modul in VHDL - Kritik erwünscht“ · FPGA, VHDL & Co. ·

  • PDF

    lab11.pdf

    <= S1; else y1 <= '1'; next_state <= S0; end if; when others => next_state <= S0; end case; end process; OUTPUT_DECODE : process (state) begin ya <= '0'; yb <= '0'; yc <= '0'; case (state) is when S0 => ya <= '1'; when S1 => yb <= '1'; when S2 => yc <= '1'; when others => ya <= '0'; yb <= '0'; yc <= '0'; end case; end process; Artix-7 11-4 www.xilinx.com/university xup@xilinx.com © copyright 2015 Xilinx Lab Workbook Sequential System Design Using ASM Charts

    in „Sequential System Design Using ASM Charts“ · FPGA, VHDL & Co. ·

  • Thread

    Choice XXX is not a locally static expression

    04", x"05", x"01", x"03" ); [/vhdl] Dann die Case-Verzweigung: [vhdl] case sv_rlg is when ac_rlg_sig_d45(4) => es_rlg_dir <= vor; when ac_rlg_sig_d45(0) => es_rlg_dir <= rueck; when others => es_fb_type <= wait_for_signal; end case; [/vhdl] Könnte es am Index liegen, der ändern

    FPGA, VHDL & Co. ·Thomas B. · ·4 Antworten

  • Datei

    echo_on_uart.vhd

    ; -- this should not be reached end if; when S2 => StateTest <= x"2"; -- debug only SMRun <= '1'; -- indicate running state machine if (TXR = '1') then TXOut <= TXOBuf; TXEn <= '1'; NState <= S3; else NState <= S2; NULL; NULL; end if; when S3

    in „bad synchronous description Wo?“ · FPGA, VHDL & Co. ·

  • Thread

    10 Bits ADC Interface mit VHDL

    ADC_inphase ; else temp1 := (others => '0'); end if ; end if ; end if ; end process Convertion ; Convertion_quadrature : Process (Clock, Reset

    ADC_quadrature ; else temp2 := (others => '0'); end if ; end if ; end if ; end process Convertion_quadrature ; Dout <= temp1 when Clock

    FPGA, VHDL & Co. ·Beruk · ·4 Antworten

  • Thread

    FSL doppel lesen in zwei Takten

    and FSL_Clk = '1') then if ( FSL_Rst = '1') then FSL_S_Read <= '0'; var <= ( others => '0'); state <= eins; else case state is when eins => if FSL_S_Exists = '1' then var <= fsl_s_data_i; FSL_S_Read <= '1';

    process ( FSL_Clk) begin if FSL_Clk'event and FSL_Clk = '1' then ... when eins => if cnt /= 0 then if FSL_S_Exists = '1' then cnt = cnt - 1; -- RISIKO? -- FSL_S_Read = '1'; ...[/vhdl]

    FPGA, VHDL & Co. ·olpo · ·4 Antworten

  • Thread

    Thyristorschaltung in KFZ-Batterieladegerät

    actually are. As a service to some people, it is a bit of good luck because it can indeed steal them when they hare effectively of cash before their next payday. As a service to others, payday loans are troublesome indebtedness instruments that run sway of help consumers. This is singularly true recompense

    payday loans, how they work, and why you should no more than use them for the right-hand reasons. When you rub in as a remedy for a payday go accommodation, the group will want you to take a even job that pays you at least a remuneration of at least a thousand dollars per month. This is important because

    Analoge Elektronik und Schaltungstechnik ·Reiner L. · ·19 Antworten

  • Thread

    Wave Simulation DEMUX

    std_logic); end demux; architecture behaviour of demux is begin process(S,X) begin case S is when "00"=> Y1 <=X; Y2<= '0'; Y3<= '0'; Y4<= '0'; when "01" => Y2<=X; Y1<='0'; Y3<='0'; Y4<='0'; when "10" => Y3 <=X; Y1 <='0'; Y2 <='0'; Y4 <='0'; when others => Y4<=X; Y1 <='0'; Y2 <=

    FPGA, VHDL & Co. ·Nico Tochowsky · ·2 Antworten

  • Datei

    artix_ftdi_fifo0.vhd

    STD_LOGIC; empty : OUT STD_LOGIC); END component; signal blinkcounter_60: unsigned(25 downto 0):=(others => '0'); signal WR_buff, TXE_buff, fail: std_logic:='0'; signal fifo_full, fifo_empty, fifo_empty_buff, fifo_rd, fifo_rd_buff, fifo_wr: std_logic:='0'; signal send_byte: unsigned(7 downto 0):=(others

    in „FT2232H Sync FIFO“ · FPGA, VHDL & Co. ·

  • Thread

    Easy question about pipeline: Is this code synthesizable?

    modules and compare them. for i in 0 to 2 loop case i is when 0 => temp1 <= a*data; when 1 => temp2 <= temp1*b; when 2 => result <= temp2*c; when others => null; end case; end loop;

    pipelines regarding the space axis. Conditional synthesis makes sence for those applications only when pipeline lengths and micro cycles have to be dynamically tuned (conditional time axis), which is rarely required. Furthermore I would recommend not to use those *temp" naming since there is nothing

    FPGA, VHDL & Co. ·Enrique · ·2 Antworten

  • Thread

    Reset Problem

    state_storage: process(reset,clock) begin if reset='1' then state <=IDLE; char_code<=(others=> '0'); char_ready<='0'; elsif (rising_edge(clock)) then state <= next_state; char_ready <= char_ready_next; char_code<=char_code_next; end if; end process state_storage

    ins IDLE springen: [c] next_state_func: process (keytrigger_next, state) begin case state is when IDLE => [/c] Der sourcecode ist weit über 100 Zeilen lang, dass will ich euch wirklich nicht zumuten...

    FPGA, VHDL & Co. ·Mel · ·5 Antworten