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PDF
xe166_um_v2.1_2008_08_vol2per.pdf
a T12 shadow transfer event is detected. Bit STE12 is cleared by hardware after the shadow transfer. A T12 shadow transfer event is a period-match while counting up or a one-match while counting down. 0 The shadow register
in „Kernel State Configuration Register KSCCFG xe164 xe166 xe164f xe16x“ · Mikrocontroller und Digitale Elektronik ·
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MCP4821-MCP4822.pdf
-1, where G is Input the selected gain (1x or 2x)N Depresents the digital Code 011 Ideal Transfer input value and n represents the number of bits of Function resolution (n = 12). 010 001 EQUATION 4-1: LSb SIZE V = - ------------ 000 OUT 2n INL < 0 DAC Output 1 LSb is the ideal voltage difference
in „Digital-Analog-Umsetzer (10V -> 1mV Auflösung)“ · Mikrocontroller und Digitale Elektronik ·
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Datei
UART_STM32F10x.c
tx.idx_in = 0; ptr_uart->info->tx.idx_out = 0; ptr_uart->info->tx.empty = true; ptr_uart->info->tx.transfer_len = 0; ptr_uart->info->rx.idx_in = 0; ptr_uart->info->rx.idx_out = 0; ptr_uart->info->rx.empty = true; ptr_uart->info->rx.transfer_len = 0; ptr_uart->info->com_break = false; if (ptr_uart->info-
in „Einbindung einer .c ohne .h“ · Mikrocontroller und Digitale Elektronik ·
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PDF
STA310AN.PDF
of the I2C bus. An Acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either the master or the slave, releases the SDA line after sending 8 bits of data. During the 9th clock pulse, the receiver pulls the SDA line to Low to acknowledge the reception of 8 bits of data. During the data transfer, the I2C slave interface of the STA310 samples the SDA line on the rising edge of the SCLKI2C clock. The SDA signal has to be stable during the rising edge of the clock and the data can change only
in „Sammelbestellung STA310 Dolby Digital Decoder“ · Markt ·
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PDF
TEA5767.pdf
It is not 2 allowed to connect the IC to an I C-bus operating at a higher clock rate. 8.1.1 Data transfer Data sequence: address, byte 1, byte 2, byte 3, byte 4 and byte 5 (the data transfer has to be in this order). The Least Significant Bit (LSB) = 0 of the address indicates a WRITE operation to the
in „Hilfe benötigt bei RDA5807SP Ansteuerung“ · Mikrocontroller und Digitale Elektronik ·
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Datei
Neu_Textdokument.txt
TIM1_OVF ; Timer 1 Overflow Handler reti ;TIM0_OVF ; Timer 0 Overflow Handler reti ;SPI_STC ; SPI Transfer Complete Handler reti ;USART_RXC ; USART TX Complete Handler reti ;USART_UDRE ; UDR Empty Handler reti ;USART_TXC ; Usart TX Complete Handler reti ;ADC_COMPLETE ; ADC Conversion Complete Handler reti
in „TWI PCF8547A HILFE“ · Mikrocontroller und Digitale Elektronik ·
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Datei
DRam.asm
COMPB ; Timer0 Compare B Handler reti rjmp TIM0_OVF ; Timer0 Overflow Handler rjmp SPI_STC ; SPI Transfer Complete Handler ;reti ;rjmp USART_RXC ; USART, RX Complete Handler reti ;rjmp USART_UDRE ; USART, UDR Empty Handler reti ;rjmp USART_TXC ; USART, TX Complete Handler reti ;rjmp ADC_COMPLETE ; ADC
in „Mega48 hängt sich auf, bitte mal über Code schauen“ · Mikrocontroller und Digitale Elektronik ·
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Datei
fet140_dma_09.c
Timer_B operates in the up mode with CCR0 defining the // sample period. DMA0 will automatically transfer each ADC12 conversion code // to memory when complete. At the end of the recording block, DMA0 will issue // an interrupt existing the function. // In the example the RAM block use to record the ADC12 data begins at 0x220. // P1.0 is toggled during DMA transfer only for demonstration purposes. // ACLK = n/a, MCLK = SMCLK = default DCO ~ 800k // //* MSP430F169 Device Required *// // // MSP430F169 // ----------------- // /|\| XIN|- // | | | // --|RST XOUT|
in „MSP430: ADC12 soll DMA triggern“ · Mikrocontroller und Digitale Elektronik ·
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Datei
RAMFEHLER.txt
Start ADC1 Software Conversion */ ADC_SoftwareStartConvCmd(ADC1, ENABLE); /* Test on DMA1 channel1 transfer complete flag */ while(!DMA_GetFlagStatus(DMA1_FLAG_TC1)); /* Clear DMA1 channel1 transfer complete flag */ DMA_ClearFlag(DMA1_FLAG_TC1);
in „STM32-F103 AD-Wandler DMA RAM OVERFLOW“ · Mikrocontroller und Digitale Elektronik ·
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Datei
fet140_i2c_09.c
called fet140_i2c_10.c. The data from the slave TX // begins at 0 and is incremented with each transfer. The received data is in // RXData and is checked for validity. If the received data is incorrect, the // CPU is trapped and the P1.0 LED will stay on. The RXRDYIFG interrupt is // used to know when
in „MSP430F4250 I2C Slave“ · Mikrocontroller und Digitale Elektronik ·
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Datei
PC_INT_TEST.asm
CompareA jmp TIMER0_COMPB ; Timer0 CompareB jmp TIMER0_OVF ; Timer0 Overflow jmp SPI_STC ; SPI Serial Transfer Complete jmp USART0_RXC ; USART0, Rx Complete jmp USART0_UDRE ; USART0 Data register Empty jmp USART0_TXC ; USART0, Tx Complete jmp ANALOG_COMP ; Analog Comparator jmp ADC_COMP ; ADC Conversion Complete
in „AVR Assembler Probleme/Fragen Interrupt“ · Mikrocontroller und Digitale Elektronik ·
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Datei
spi2in.vhd
SCLK : out STD_LOGIC; -- SPI Clock SS : out STD_LOGIC; -- Slave Select TX_Start : in STD_LOGIC; -- Transfer Init Flag TX_Done : out STD_LOGIC; -- Treansfer Finish Flag clk : in STD_LOGIC -- Oscillator Clock ); end spi2in; architecture Behavioral of spi2in is signal delay : integer range 0 to (Quarz_Taktfrequenz
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Datei
Code1.txt
u_pUSART0->US_TTGR = 0; //Set the USART mode u_pUSART0->US_MR = 0x08c0; //Enable the RX and TX PDC transfer requests // u_pPDC0->PDC_PTCR = AT91C_PDC_TXTEN | AT91C_PDC_RXTEN; //Enable usart - enable RX receiver and TX transmiter u_pUSART0->US_CR = 0x50; } void InitUSART1(void) { u_pPioA->PIO_PDR = BIT5
in „Data aus USART vom SAM7-EX256 lesen“ · Mikrocontroller und Digitale Elektronik ·
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Datei
Code1.c
u_pUSART0->US_TTGR = 0; //Set the USART mode u_pUSART0->US_MR = 0x08c0; //Enable the RX and TX PDC transfer requests // u_pPDC0->PDC_PTCR = AT91C_PDC_TXTEN | AT91C_PDC_RXTEN; //Enable usart - enable RX receiver and TX transmiter u_pUSART0->US_CR = 0x50; } void InitUSART1(void) { u_pPioA->PIO_PDR = BIT5
in „Data aus USART vom SAM7-EX256 lesen“ · Mikrocontroller und Digitale Elektronik ·
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Datei
test.asm
CompareA jmp TIMER0_COMPB ; Timer0 CompareB jmp TIMER0_OVF ; Timer0 Overflow jmp SPI_STC ; SPI Serial Transfer Complete jmp USART1_RXC ; USART1, Rx Complete jmp USART1_UDRE ; USART1 Data register Empty jmp USART1_TXC ; USART1, Tx Complete jmp ANALOG_COMP ; Analog Comparator jmp ADC_COMP ; ADC Conversion Complete
in „AVR Assemblersprache zu Opcode nicht nachvollziehbar“ · Mikrocontroller und Digitale Elektronik ·
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PDF
KPCI-488LPA-900-01__A_-_Dec_2008__User_.pdf
timeout error SETINPUTEOS Description This function sets the terminating character for input data transfer. Syntax Microsoft C/C++ and Borland C++ void setinputEOS (long int eos_c) Visual Basic call setinputEOS (ByVal eos_c As Long) Parameters eos_c: the terminating character for input data transfer 1-
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xmega_a1.pdf
access all the peripherals through their I/O memory registers, and the DMA may be used for automatic transfer of data to/from communication modules, as well as automatic data retrieval from ADC conversions, data transfer to DAC conversions, or data transfer to or from port pins. A wide range of transfer triggers is available from the peripherals, Event System and software. Each DMA channel has different transfer triggers. To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the first is finished and vice versa. The DMA controller can read from
in „Welchen Wert hat der Pull-up-Widerstand dieses XMega?“ · Mikrocontroller und Digitale Elektronik ·
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MCP41HVX1.pdf
For Measured: (VW(@FS) - VW(@ZS)) / # ofSR (VW(@FS) - VW(@ZS)) / 255 INL < 0 111 111 Actual 110 transfer 110 Actual function transfer 101 function 101 Wiper 100 Ideal transfer Wiper 100 Code function Code 011 011 Ideal transfer 010 function Wide code, > 1 LSb 010 001 001 000 000 Narrow code < 1 LSb INL
in „MCP41HVX READCMD falsch verstanden??“ · Mikrocontroller und Digitale Elektronik ·
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PDF
W83627HF_datasheet.pdf
the FDC. At this data rate the FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk. 3.1.6 FDC Core The W83627HF FDC is capable of performing twenty commands. Each command is initiated by a multi- byte transfer from the microprocessor. The result can also be a
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R8C22-23_Group_Hardware_Manual.pdf
Transfer TRDGRB0 register n1 n2 n3 n2 n1 Transfer with timing set by Transfer by Transfer by Transfer with timing set by CMD1 to CMD0 bits underflow in TRD1 underflow in TRD1 CMD1 to CMD0 bits register because
in „Fragen zu Renesas µC (R5F2122CKFP)“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Schwingkond-53278649.pdf
broadband noise into the baseband. Similarly for CDS, there is a zero at the origin for the baseband transfer function that cancels any DC offset and significantly reduces the 1/f noise. However, the folded components will be scaled by different but comparable transfer functions to those described in the
in „DC-Messverstärker (Chopper) mit Kapazitätsdioden (diskret)“ · Analoge Elektronik und Schaltungstechnik ·
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Datei
I2C.c
util/delay.h> #define F_CPU 18.432E6UL #define SLA 0x20 //Adresse des Terminals #define W 0 //Data transfer direction WRITE #define R 1 //Data transfer direction READ //General Master staus codes #define START 0x08 //START has been transmitted #define REP_START 0x10 //Repeated START has been transmitted
in „I2C Problem (Anfänger )“ · Mikrocontroller und Digitale Elektronik ·
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Datei
test6-spi-dma.cc
SPI_CR1_MODE(mode) | SPI_CR1_BR_by4; SPI2->CR2 = SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN; } unsigned spi_transfer(volatile void *data, unsigned count) { GPIOB->BRR = 1<<12; // activate SS DMA1_Channel4->CMAR = (unsigned)data; // setup memory buffer DMA1_Channel5->CMAR = (unsigned)data; DMA1_Channel4->CNDTR =
in „STM32 SPI1 und DMA (für Rx und Tx)“ · Mikrocontroller und Digitale Elektronik ·
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Datei
Max7313.c
************************************************ Issues a start condition and sends address and transfer direction. return 0 = device accessible, 1= failed to access device *************************************************************************/ void i2c_start(unsigned char address) { uint8_t twst;
in „Max7313 I2C Probleme.“ · Mikrocontroller und Digitale Elektronik ·
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Datei
test.asm
disabled ; - SPI module enabled ; - most-significant bit is transmitted first ; - master mode ; - transfer mode: leading edge as falling, setup and trailing edge as rising, sample ; - prescaler: Clk_PER/16 ldi r16, 0b01011001 sts SPID_CTRL, r16 ; set up interrupt control register for SPID ; - interrupt
in „[asm] ST7565R Ansteuerung“ · Mikrocontroller und Digitale Elektronik ·
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Datei
USB-IO__LUFA_.c
* Process Generic Report Data */ ProcessGenericHIDReport(GenericData); } /* Finalize the stream transfer to send the last packet */ Endpoint_ClearOUT(); } Endpoint_SelectEndpoint(GENERIC_IN_EPADDR); /* Check to see if the host is ready to accept another packet */ if (Endpoint_IsINReady()) { /* Create
in „ATmega32U2 USB-Kommunikation“ · Mikrocontroller und Digitale Elektronik ·
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PDF
VWM200-01P.pdf
mounting s -isolated DCB ceramic base plate IGSS V GS= ±20 V; VDS= 0 V 0.2 µA with optimized heat transfer Q g a 430 nC Q gs V = 10 V; V = 80 V; I = 200 A 90 nC Q gd GS DS D 180 nC t h 40 ns td(on) 100 ns td(off) VGS 10 V; V DS= 50 V; 260 ns tf p D = 50 A; G = 2.7 Ω 100 ns VF (diode) F = 100 A; GS= 0 V 1.0 1.5 V trr (diode) F = 40 A; -di/dt = 200 A/µDS V = 30 V 100 ns R 0.26 K/W R thJC with heat transfer paste 0.51 K/W thJH IXYS reserves the right to change limits, test conditions and dimensions. 0 © 2006 IXYS All rights reserved 1 - 2 Advanced Technical Information VWM 200-01P Module EquivalentCircuitsforSimulation
in „Umrichter für E-Kart Anwendung 60V / 120A“ · Mikrocontroller und Digitale Elektronik ·
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PDF
_Transistortester-Hardware.pdf
mehr Funktionen bieten. Dazu entstand dazu bei mir eine einseitige Leiterplatte 60x80mm in Toner-Transfer- Technik für ein preiswertes Gehäuse. Diese stelle ich mit den erforderlichen Unterlagen für eventuelle Nachbauer gerne zur Verfügung. Wenn Fragen auftauchen, versuche ich gerne zu helfen. Selbstbau
in „Transistortester AVR - Hardware“ · Mikrocontroller und Digitale Elektronik ·
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Datei
i2c-hd44780.c
void set_pcf8574(uint8_t data) { i2c_start(LCD_I2C_ADDR); i2c_write(data); i2c_stop(); } void lcd_transfer_4bit(uint8_t data, uint8_t cd) { uint8_t out = 0; uint8_t rs = 0; if(cd) rs=LCD_RS; //4 upper bits if(data & (1<<4)) out |= LCD_D4; if(data & (1<<5)) out |= LCD_D5; if(data & (1<<6)) out |= LCD_D6
in „STM32F407, I2C LCD, Initialisierung“ · Mikrocontroller und Digitale Elektronik ·
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Datei
InitSPI_LCD.c
baudrate = MCK/8 = 48054841/8 = 6006855 baud //(AT91C_SPI_BITS & (AT91C_SPI_BITS_9)) | // Bits per Transfer (9 bits) //(AT91C_SPI_CSAAT & (0x0 << 3)) | // Chip Select Active After Transfer (is active after xfer)/ //(AT91C_SPI_NCPHA & (0x0 << 1)) | // Clock Phase (data captured on falling edge) //(AT91C_SPI_CPOL
in „SPI-Initialisierung von zwei Geräte über den gleichen Bus“ · Mikrocontroller und Digitale Elektronik ·
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Datei
receive.c
= buf[0]; uint16_t res; uint8_t rx[2] = {0, 0}; printf("cmd: "); print_cmd(cmd); struct spi_ioc_transfer tr = { .tx_buf = (unsigned long)tx, .rx_buf = (unsigned long)rx, .len = 2, .delay_usecs = 0, .speed_hz = SPEED, .bits_per_word = 8, }; ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); if(ret < 0) { printf
in „RaspberryPi + RFM01: FIFO mode gibt keine Daten“ · Mikrocontroller und Digitale Elektronik ·
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PDF
intro.pdf
the context with other elements of the Embedded Software. A usual used debugger is not able to transfer the Data amount about longer times of observation. A faster transfer rate is neccessary. Also interesting in this Point is a independent realtime clock. Modern Trace-Debuggers are able to do this
in „Linux CAN Sniffer als realtime debugger“ · Mikrocontroller und Digitale Elektronik ·
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PDF
LCD1602-datasheet.pdf
L H--Read L--Write 6 E H,H-L Enable Signal 7 DB0 H/L 8 DB1 H/L 9 DB2 H/L Data bus used in 8 bit transfer 10 DB3 H/L 11 DB4 H/L 12 DB5 H/L Data bus for both 4 and 8 bit transfer 13 DB6 H/L 14 DB7 H/L 15 BLA -- BLACKLIGHT +5V 16 BLK -- BLACKLIGHT 0V- 6.0 BLOCK DIAGRAM 7.0 POWER SUPPLY BLOCK DIAGRAM 1602A
in „LCD1602 extern mit 5V versorgen (weil msp430@3.6V)“ · Mikrocontroller und Digitale Elektronik ·
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PDF
LCD_DISPLAY.pdf
L H--Read L--Write 6 E H,H-L Enable Signal 7 DB0 H/L 8 DB1 H/L 9 DB2 H/L Data bus used in 8 bit transfer 10 DB3 H/L 11 DB4 H/L 12 DB5 H/L Data bus for both 4 and 8 bit transfer 13 DB6 H/L 14 DB7 H/L 15 BLA -- BLACKLIGHT +5V 16 BLK -- BLACKLIGHT 0V- 6.0 BLOCK DIAGRAM 7.0 POWER SUPPLY BLOCK DIAGRAM 1602A
in „Probleme mit HD44780 1602 LCD Module“ · Mikrocontroller und Digitale Elektronik ·
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PDF
run-kommandos.pdf
Advanced UserAccounts netplwiz Authorization Manager azman Backup and Restore sdclt Bluetooth File Transfer fsquirt Calculator calc Certificates certmgr Change Computer Performance Settings systempropertiesperformance Change Data Execution Prevention Settings systempropertiesdataexecutionprevention Change
in „Liste der Tools von WinXP gesucht“ · PC Hard- und Software ·
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PDF
MPVD7N65.pdf
VGS30V - - 100 nA Drain-source on-resistance R DS(ON) VGS10V, I D3.5A 1.35 (Note 3) Forward transfer conductance g fs VDS10V, I D=3.5A - 4 - S Input capacitance Ciss - 760 1046 V =25V, V =0V, Output capacitance Coss DS GS - 67 92 pF f=1.0MHz Reverse transfer capacitance Crss - 9 12 Turn-on delay
in „Unbekannte Bauelemente“ · Analoge Elektronik und Schaltungstechnik ·
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PDF
DM00043574.pdf
, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel • Memory-to-memory transfer • Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral
in „STM32F3 Discovery als USB Keyboard“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATMega164_324_644_1284pa.pdf
/P 18. SPI – Serial Peripheral Interface 18.1 Features Full-duplex, Three-wire Synchronous Data Transfer Master or Slave Operation LSB First or MSB First Data Transfer Seven Programmable Bit Rates End of Transmission Interrupt Flag Write Collision Flag Protection Wake-up from Idle Mode Double Speed (
in „Hilfe bei AD-Wandler!“ · Mikrocontroller und Digitale Elektronik ·
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PDF
datasheet_SC16IS750.pdf
acknowledge when it can no longer accept additional data bytes. This occurs after an attempted transfer that cannot be accepted. 10.2 Addressing and transfer formats Each device on the bus has its own unique address. Before any data is transmitted on the bus, the master transmits on the bus the address
in „UART_Initialisierung“ · Mikrocontroller und Digitale Elektronik ·
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PDF
LSM303C_datasheet.pdf
. . . . . . . . . . . . . . . 25 Table 14. Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 25 Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . .
in „STM32F05 SPI 3 Wire Verbindung mit Accelerometer“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Spice_3f3_Users_Manual.pdf
the poles and zeros of the transfer function. Two types of transfer functions are allowed : one of the form (output voltage)/(input voltage) and the other of the form (output voltage)/(input current). These two types of transfer functions
in „Potenzierender Operationsverstärker, Daten Diode“ · Analoge Elektronik und Schaltungstechnik ·
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PDF
AT89S8252_Datasheet_doc0401.pdf
WCOL Write Collision Flag. The WCOL bit is set if the SPI data register is written during a data transfer. During data transfer, the result of reading the SPDR register may be incorrect, and writing to it has no effect. The WCOL bit (and the SPIF bit) are cleared by reading the SPI status register with
in „lichtschranke mit zählfunktion einer umdrehung“ · Mikrocontroller und Digitale Elektronik ·
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PDF
mc68hc11a1.pdf
5 4 3 2 1 LSB SAMPLE INPUT MSB 6 5 4 3 2 1 LSB (CPHA = 1) DATA OUT SS (TO SLAVE) 3 SLAVE CPHA=1 TRANSFER IN PROGRESS 2 MASTER TRANSFER IN PROGRESS 4 1 SLAVE CPHA=0 TRANSFER IN PROGRESS 5 1. SS ASSERTED 2. MASTER WRITES TO SPDR 3. FIRST SCK EDGE 4. SPIF SET 5. SS NEGATED SPI TRANSFER FORMAT 1 Figure 10
in „mc68hc11a1fn-uC-8bit“ · Markt ·
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PDF
AT89S8252.pdf
WCOL Write Collision Flag. The WCOL bit is set if the SPI data register is written during a data transfer. During data transfer, the result of reading the SPDR register may be incorrect, and writing to it has no effect. The WCOL bit (and the SPIF bit) are cleared by reading the SPI status register with
in „UART_ Werte empfangen???“ · Mikrocontroller und Digitale Elektronik ·
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PDF
AT89S8252.pdf
WCOL Write Collision Flag. The WCOL bit is set if the SPI data register is written during a data transfer. During data transfer, the result of reading the SPDR register may be incorrect, and writing to it has no effect. The WCOL bit (and the SPIF bit) are cleared by reading the SPI status register with
in „I2C Anschluß AT89S8252“ · Mikrocontroller und Digitale Elektronik ·
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PDF
doc0401.pdf
WCOL Write Collision Flag. The WCOL bit is set if the SPI data register is written during a data transfer. During data transfer, the result of reading the SPDR register may be incorrect, and writing to it has no effect. The WCOL bit (and the SPIF bit) are cleared by reading the SPI status register with
in „IDE für 8051“ · Mikrocontroller und Digitale Elektronik ·
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PDF
SIM800_Hardware_Design_V1.09.pdf
range Normal operation:-40°C ~ +85° C Storage temperature -45C ~ +90° C GPRS data downlink transfer: max. 85.6 kbps GPRS data uplink transfer: max. 85.6 kbps Coding scheme: CS-1, CS-2, CS-3 and CS-4 GPRS PAP protocol for PPP connect Integrate the TCP/IP protocol. Support Packet Broadcast
in „SIM800L Verbindung instabil“ · Mikrocontroller und Digitale Elektronik ·
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PDF
AS1130_Datasheet_EN_v5__1_.pdf
. The bus conditions are defined as: Bus Not Busy. Data and clock lines remain HIGH. Start Data Transfer. A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop Data Transfer. A change in the state of the data line, from LOW to HIGH, while the
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PDF
AN10025_1.pdf
interface of ISP1160x is designed for a simple direct connection with a RISC processor. The data transfer can be done in the programmed I/O (PIO) or direct memory access (DMA) mode. The estimated maximum data transfer rate on ISP1160x’s generic processor bus is approximately 15 Mbyte/s. This is based on an ISP1160x internal clock frequency value of 48 MHz. To achieve the maximum data transfer rate on the host processor bus, ISP1160x contains ping pong structured RAM that allows alternative access from the RISC processor or from the internal Host Controller. The Host Controller uses 2 kbytes
in „USB Host Controller (ISP1160) an StrongARM 1110 anbinden“ · Mikrocontroller und Digitale Elektronik ·
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PDF
AVR311_Using_the_TWI_module_as_I2C_slave_doc2565.pdf
the SCL and SDA lines while a Slave device is only allowed to issue data on the SDA line. Data transfer is always initiated by a Bus Master device. A high to low transition on the SDA line while SCL is high is defined to be a START condition or a repeated start condition. Figure 2. TWI Address and Data
in „TWI Interrupt“ · Mikrocontroller und Digitale Elektronik ·