Suchergebnisse für "when others"

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3880 Treffer für when others Suchergebnisse für "when others"

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  • Thread

    Vereinfachung einer Beschreibung

    [vhdl] process(clk) begin wait until rising_edge(clk); case s is when a => if iEna='1' then s <= b; end if; when b => if iEna='0' then s <= a;

    myEna <= '1'; s <= c; end if; when c => if iEna='0' then s <= d; end if; when d => if other_ena='0' then s <= a; end if

    FPGA, VHDL & Co. ·Joe · ·8 Antworten

  • Thread

    FPGA Clockgenerierung

    clockCnt <= clockCnt + 1; --sonst counter erhöhen end if; when GLITCHING => if (clockCnt = definedGlitchCnt) then --dauer der glitche -> flanke oCLK <= not oCLK; clockCnt <= (others => '0');

    else clockCnt <= clockCnt + 1; --counter erhöhen end if; when POST_TRIGGER => if (clockCnt = definedClockCnt) then --normaler takt oCLK <= not oCLK; clockCnt <= (others => '0');

    FPGA, VHDL & Co. ·Igor · ·7 Antworten

  • Datei

    ether_tx.vhd

    <= crc32_n(31 downto 24); tx_en1 <= '1'; when others => data_o1 <= (others => '0'); tx_en1 <= '0'; end case; end if; end process; --calculate crc process (wclk) begin if rising_edge(wclk) then if nibbleout = '1' then if state_txout = pre0 then crc32 <= (others => '1'); elsif state_txout=send then crc32 <= crc(fifo_out, crc32); end if; end if; end if; end process; crc32_n <= not crc32; -- data_o2 <= data_o1 when nibbleout = '1' else "XXXX"& data_o1(7 downto

    in „VHDL timing in GMII auf Spartan6“ · FPGA, VHDL & Co. ·

  • Datei

    TopAS21.vhd

    X"48" => StRcntr1 <= 5; WHEN X"50" => StRcntr1 <= 6; WHEN X"40" =>--keine ref anfahren REF01 <= '1'; StRcntr1 <= 9; WHEN OTHERS => StRcntr1 <= 0; END CASE;--RefBefehl WHEN 2 => --Ausführung RefBefehl:41= X Allein REFRUN2 <= '1'

    in „Post-Map simulation mit ModelSim“ · FPGA, VHDL & Co. ·

  • Thread

    Frage zu variable counter : std_logic_vector(2 downto 0) := "100";

    when others => null; end case; counter := counter - 2; end if; -- zusammenfuehren der Kanaele: Es geht ein Schritt zurueck if counter <= "010" then case state is

    when others => null; end case; counter := counter + 2; end if; end process; end Behavioral; [/vhdl]

    FPGA, VHDL & Co. ·Reinhard J. · ·7 Antworten

  • Thread

    unsigned => hex

    "; when others => return "XXXX"; end case; end function;

    " & bin_in; when "1001" => shiftreg <= "100" & bin_in; when others => shiftreg <= shiftreg(2 downto 0) & bin_in; end case; end if; end if; end process; bcd_out <= shiftreg

    FPGA, VHDL & Co. ·Gast · ·5 Antworten

  • Thread

    Lockerer Counter auf VHDL

    architecture Behavioral of CounterMdl is signal tempNum: STD_LOGIC_VECTOR (Bits-1 downto 0) := (others => '0'); begin process(clk) begin if (clk='1' and clk'event) then tempNum <= tempNum + 1; output <= tempNum; end if; end process; end Behavioral; -------------

    architecture Behavioral of CounterMdl is > signal tempNum: STD_LOGIC_VECTOR (Bits-1 downto 0) := (others => '0'); > begin > process(clk) > begin > if (clk='1' and clk'event) then > tempNum <= tempNum + 1; > output <= tempNum; > end if; > end process; > end Behavioral

    FPGA, VHDL & Co. ·Samer Afach · ·18 Antworten

  • Thread

    Durch 10 teilen

    " when "0100", "1011011" when "0101", "1011111" when "0110", "1110010" when "0111", "1111111" when "1000", "1111011" when "1001", "0000000" when others; SEGA

    " when "0100", "1011011" when "0101", "1011111" when "0110", "1110010" when "0111", "1111111" when "1000", "1111011" when "1001", "0000000" when others; SEGA

    FPGA, VHDL & Co. ·Bastelboy · ·31 Antworten

  • Datei

    ansteuerung.vhdl

    IS WHEN "000000" => rec_cnt<="000001"; WHEN "000001" => rec_cnt<="000010"; WHEN "000010" => rec_cnt<="000011"; WHEN "000011" => rec_cnt<="000100"; WHEN "000100" => rec_cnt<="000101";clk_out_i <= '1'; WHEN "

    in „Probleme mit Ansteuerung AD5290“ · Mikrocontroller und Digitale Elektronik ·

  • Datei

    la_register.vhd

    <= to_integer(unsigned(data)); when others => null; end case; when others => null; end case; ------------------------------------------------------------------- -- READ MODE ------------------------------------------------------------

    in „Modelsim Problem- bidirektionaler Bus“ · FPGA, VHDL & Co. ·

  • Datei

    pseuzufgen01.vhd

    then -- wenn QINT15 den Wert 000000000000001 hat, wird der Zyklenzähler zurückgesetzt! B_COUNT <= (others => '0'); else B_COUNT <= B_COUNT + 1; -- gibt an nach wie viel Taktzyklen sich die Periode wiederholt !!! end if; end if; when others => if QINT16 = "0000000000000000" then -- wenn alle Registerausgänge

    in „flexibler Pseudozufallszahlengenerator! was mache ich falsch?“ · FPGA, VHDL & Co. ·

  • Datei

    pseuzufgen01.vhd

    then -- wenn QINT15 den Wert 000000000000001 hat, wird der Zyklenzähler zurückgesetzt! B_COUNT <= (others => '0'); else B_COUNT <= B_COUNT + 1; -- gibt an nach wie viel Taktzyklen sich die Periode wiederholt !!! end if; end if; when others => if QINT16 = "0000000000000000" then -- wenn alle Registerausgänge

    in „Fehlermeldung ISE: Can not determine the "others" values in aggregate ?“ · FPGA, VHDL & Co. ·

  • Thread

    Uart Daten werden Falsch übertragen

    DataBitCnt_reg; data_next <= data_reg; rx_done_tick <='0'; case s_reg is when idle => if RXD='0' then s_next <= start; TickCnt_next <= (others=>'0'); end if; when start => if (RX_tick = '1') then if TickCnt_reg=7 then s_next <= data; TickCnt_next <= (others=>'0'); DataBitCnt_next <= (others=>'0'); else TickCnt_next <= TickCnt_reg + 1; end if; end if; when data

    FPGA, VHDL & Co. ·Maximilian S. · ·9 Antworten

  • Datei

    BCDto7SegmentDecoder.vhd

    , 3 => ledOff, 4=> ledOff, others => ledOn) when "0100", (1 => ledOff, 4=> ledOff, others => ledOn) when "0101", (1 => ledOff, others => ledOn) when "0110", (0 => ledOn, 1 => ledOn, 2 => ledOn, others => ledOff) when "0111", (others => ledOn) when "1000", (4 => ledOff,others => ledOn) when "1001", (others => ledOff) when others; end RTL;

    in „Meinung zum Anfänger-Code“ · FPGA, VHDL & Co. ·

  • Thread

    hexadezimalzahl drehung

    process( slv_reg_read_sel, slv_reg0 ) is begin case slv_reg_read_sel is when "1" => slv_ip2bus_data <= slv_reg0; when others => slv_ip2bus_data <= (others => '0'); end case; end process SLAVE_REG_READ_PROC; ------------------------------------------

    IP to Bus signals ------------------------------------------ IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0'); IP2Bus_WrAck <= slv_write_ack; IP2Bus_RdAck <= slv_read_ack; IP2Bus_Error <= '0'; end IMP;

    FPGA, VHDL & Co. ·reno kortes · ·4 Antworten

  • Thread

    Addition & Multiplikation mit FPGA

    when others => error <= '0'; zaehler <="000"; end case; end process; [/vhdl] MFG Falk

    zustand <= ZUSTAND_1; end if; ------------------------------------------ when others => NULL; end case; end if; end process; [/vhdl] Was hier klar sein muss, "zustand" und "led" werden als Register gebaut. Es sind damit Speicherelemente, die den Wert nur bei

    FPGA, VHDL & Co. ·D. E. · ·58 Antworten

  • Thread

    State machine für SPI

    StateControl process. SIGNAL dataBuffer1, dataBuffer2 : STD_LOGIC_VECTOR(regBits-1 downto 0) := (others => '0'); SIGNAL temp : INTEGER := 0; -- states description: -- I defined here a Zero state as the state where both SPI_SCK and AD_CONV = 0. -- START_STATE: I wrote this

    are reset to avoid having latches, but not the one getting counted over in the current state when START_STATE => AD_CONV_WAIT_COUNTER_VAR := 0; SPI_CLK_EN_COUNTER_VAR := 0; DATA_AC1_COUNTER_VAR := 0; DATA_AC_WAIT_COUNTER_VAR := 0; DATA_AC2_COUNTER_VAR

    FPGA, VHDL & Co. ·Samer Afach · ·26 Antworten

  • Datei

    Main.vhd

    implementierte, sekundenweise Ausgabe TEST <= '1'; DEZIMALZIFFERN <= to_bcd(UMDREHUNGEN); UMDREHUNGEN <= (others => '0'); else TEST <= '0'; end if; end if; end process UMDREHUNGEN_DETECT; -- Sieben Segment Codierer SEVEN_SEG: process(LED) begin case LED is when X"0" => SEG_OUT <= "0000001"; --0 when X"1" => SEG_OUT

    in „Feedback für Drehgeber Design“ · FPGA, VHDL & Co. ·

  • Thread

    VHDL Newbie -->Kontrolle VHDL COde

    dabei ? Zeig doch mal, was du schon hast... Ich würde es mal so ansetzen: [vhdl] Latchout <= (others => '0') when (Reset = '1') else DB when (ADR7 = "00010100" AND IORQ = '0' AND WR = '0') else Latchout ; [/vhdl] BTW: hier im Forum kannst du mit den Tags [ vhdl ]

    <= (others => '0') when (Reset = '0') else -- DB when (ADR7 = "00010100" AND IORQ = '0' AND WR = '0') -- else Latchout ; CSROM <= MEMRD when ((ADR15="1110" OR ADR15="1111")

    FPGA, VHDL & Co. ·Ralph H. · ·23 Antworten

  • Thread

    VHDL ROM Component: Sollte 1 geben, gibt aber X

    my_state <= write_back; when others => my_state <= halt; end case; when write_back => procouta <= accu; my_State <= advance_PC; when advance_PC => pc <= pc + 1; my_state <

    --Bestimem Op-Code case decodeOp(instruction(11 downto 8)) is when OP_OR => accu <= accu or getValue(instruction); my_state <= write_back; when others => my_state <= halt; end case; when write_back => procouta

    FPGA, VHDL & Co. ·Rene · ·7 Antworten

  • Thread

    VGA-Signal -Übertragungsprobleme.

    process; inScreen <= dispVertical and dispHorizontal; aktColumn <= aktHorizontal-144 when dispHorizontal='1' else 0; aktLine <= aktVertical-31 when dispVertical='1' else 0; Line <= aktLine; Column <= aktColumn; RedOut <= RedIn when inScreen='1' else '0'; GreenOut <= GreenIn when inScreen='1' else '0'; BlueOut <= BlueIn when inScreen='1' else '0'; Hsync <= syncH; Vsync <= syncV; end Behavioral; [/vhdl]

    FPGA, VHDL & Co. ·Mike · ·12 Antworten

  • Datei

    Noise_Shaper.vhd

    LT2_old <= (others => '0'); LT3_old <= (others => '0'); LT4_old <= (others => '0'); else case state_reg is when 0 => if(new_data = '1') then state_reg <= 1; MAC_exec <= '0'; MAC_preload <= '0'; program_counter <= 0;

    in „Noise Shaper in VHDL“ · FPGA, VHDL & Co. ·

  • Datei

    dmcache.vhd

    cacheLines(to_integer(unsigned(req_line))); with req_word select temp_data <= temp_line(15 downto 0) when "00", temp_line(31 downto 16) when "01", temp_line(47 downto 32) when "10", temp_line(63 downto 48) when others; isvalid <= valid(to_integer(unsigned(req_line))); process begin if (reset = '1') then

    in „cachemodul, Simulation ok, aber auch bereit für die Synthese?“ · FPGA, VHDL & Co. ·

  • Datei

    Main.vhd

    ; else F_ZUSTAND <= GO; end if; when NEWHIGHSCORE => LCD_SEL <= 5; EN_WR_SCORE_REG <= '1'; when others => LCD_SEL <= 1; end case; end process FSM; LCD_MUSTER: process(LCD_SEL, POS1, POS2, POS3, POS4, ASK_VALUE, HEX_POS1, HEX_POS2) begin

    in „[VHDL] Komponenten Einbinden und wegoptimieren von Signalen verhindern“ · FPGA, VHDL & Co. ·

  • Thread

    FF/Latch Warnung bei LCD Display

    Effekte beobachten: [vhdl] --multiplexer richtig schalten with AKT_STATUS select SCHALT <= '1' when INIT, '0' when others; with SCHALT select LCD_E <= LCD_E0 when '0', --zum übertragen LCD_E1 when others; --zum Initialisieren --gibt Aufschluss darüber, ob Daten oder Befehle übertragen werden --RS=0 für Befehle und RS=1 für Daten with AKT_STATUS select LCD_RS <= '0' when FUNCTION_SET| ENTRY_SET | SET_DISPLAY |CLEAR_DISPLAY |SET_ADDR, '1' when others; [/vhdl] Denn die Umschaltung zwischen den Zuständen geschieht nicht in 0.0ns, sondern es dauert dank Laufzeiten und

    FPGA, VHDL & Co. ·Johannes · ·43 Antworten

  • Datei

    LCD-Componenten.txt

    done => state <= idle; end case; end if; end process; with state select write_done <= '1' when done, '0' when others; with state select lcd_e_w <= '1' when s2|s6, '0' when others; with state select lcd_rw <= '1' when idle|s4|s8|done, '0' when others; with state select lcd_db_w <= db(7 downto

    in „LCD Ansteuerung mit spartan-3E starter“ · FPGA, VHDL & Co. ·

  • Thread

    bleibe in Zustand hängen, warum?

    when "10111" => FOLGE_Z <= Z_LEFT; when "01111" => FOLGE_Z <= Z_RIGHT; when others => FOLGE_Z <= Z0; end case; when Z_UP => FOLGE_Z <= Z

    when "11011" => FOLGE_Z <= Z_DOWN; when "10111" => FOLGE_Z <= Z_LEFT; when "01111" => FOLGE_Z <= Z_RIGHT; when others => FOLGE_Z <= Z0;

    FPGA, VHDL & Co. ·Ole · ·11 Antworten

  • Thread

    VHDL Problem mit IF

    probiers mal mit einem case statment in der clock also if rising_edge(clk) then case xy is when "0000" => r<='1'; when "" => when others => end case; end if;

    g<='0'; end if; when others => end case; end if; /vhdl

    FPGA, VHDL & Co. ·Kaffeetasse · ·15 Antworten

  • Thread

    Zaehler so langsam?

    FULL <= '0'; -- clear full flag end if; when others => adress_cnt <= adress_cnt + 1; -- no overflow increase adress_cnt end case; end if; end if; end if; end

    "; DOUT <= DIN(95 downto 88); when others => ramenable_int <= "000000000000"; DOUT <= DIN(7 downto 0); end case; end if; end if; end process; end RTL; [/vhdl] Dirk

    FPGA, VHDL & Co. ·Dirk · ·24 Antworten

  • Thread

    VHDL Codeergänzung um Pushbutton zu entprellen

    "0100100" when "0101", -- 5 "0100000" when "0110", -- 6 "0001111" when "0111", -- 7 "0000000" when "1000", -- 8 "0000100" when "1001", -- 9

    "0111000" when "1111", -- F "1111111" when others; -- turn off all LED ausgang_anode <= "1110"; --clk_proc: process(clk, reset) clk_proc: process(clk, reset, taster) begin

    FPGA, VHDL & Co. ·Tob M. · ·4 Antworten

  • Datei

    SweepGen.vhd

    _Process : process(CLK200) begin if rising_edge(CLK200) then if Reset = '0' then DelayOBUFIn <= (others=>'0'); BitCount <= 0; LED <= '1'; STATE <= SetCalibration; else LED <= '0'; case STATE is when SetCalibration => --PLL Locked? if Locked_i = '1' then STATE <= DoCalibration; end if; when DoCalibration => STATE <= CalibrationDone; when CalibrationDone => DelayOBUFIn <= (others=>'0'); if ClkCount = 5 then ClkCount <= 0; STATE <= SetData; else ClkCount <= ClkCount + 1; end if; when SetData => if MuxOSel = 15 and BitCount = 7 then MuxOSel

    in „Delay Line Ausgangssignal falsch“ · FPGA, VHDL & Co. ·

  • Thread

    Entfernen von Spikes ohne Eintakten

    Zählerstandes end if; end process; with counter_i select reset_enable_i <= '0' when "0000000000", '1' when others;[/vhdl] meine zielplattform ist ein lattice machxo 2280C. ich habe meine asynchronen I2S signale alle 2mal eingetaktet. der takt TXC läuft mit 25 MHz

    Systemtakt? Woher kommt der TXC? BTW: [vhdl] with counter_i select reset_enable_i <= '0' when "0000000000", '1' when others; [/vhdl] Das könntest du leserlicher so schreiben: [vhdl] reset_enable_i <= '0' when counter_i="0000000000" else '1'; [/vhdl] Und auch das sieht sehr

    FPGA, VHDL & Co. ·Andi Z. · ·15 Antworten

  • Datei

    adcamp01.vhd

    x"2B", init(0) when x"2C", init(0) when x"2D", init(0) when x"2E", init(0) when x"2F", '0' when others; with counter3 select ad_conv <= '1' when x"01", '0' when others; --zum testen with counter3 select ad_conv2 <= '1'

    in „Spartan 3e - ADC“ · FPGA, VHDL & Co. ·

  • Thread

    Unterschied von selektiven Signalzuweisungen und cases in Prozessen

    Was ist eigentlich der Unterschied zwischen [vhdl] with mode select signal1 <= signal1a when modeA, signal1b when modeB, signal1c when modeC; with mode select signal2 <= signal2a when modeA, signal2b when modeB, signal2c when modeC; [/vhdl] und [vhdl] process (mode, signal1a, signal1b, signal1c, signal2a, signal2b, signal2c ) begin case mode is when modeA =>

    FPGA, VHDL & Co. ·Andreas D. · ·4 Antworten

  • Thread

    UART empfangen auf FPGA

    when "0100" => TXD <= S_OUTPUT_BUFFER(3); when "0101" => TXD <= S_OUTPUT_BUFFER(4); when "0110" => TXD <= S_OUTPUT_BUFFER(5); when "0111" => TXD <= S_OUTPUT_BUFFER(6); when "1000" => TXD <= S_OUTPUT_BUFFER(7); when "1001" => TXD <= '1'; when others => NULL; end case; else TXD <= '1'; end if; end if

    FPGA, VHDL & Co. ·Hans Hirsch · ·42 Antworten

  • Thread

    Statemaschine fehler!

    ; when ras2 => usb_next_stat <= ras3; when ras3 => usb_next_stat <= ras4; when ras4 => usb_next_stat <= ras5; when ras5 => usb_next_stat <= idle; when others => usb_next_stat

    <= ras2; when ras2 => usb_next_stat <= ras3; when ras3 => usb_next_stat <= ras4; when ras4 => usb_next_stat <= ras5; when ras5 => usb_next_stat <= idle; when others => usb_next_stat

    FPGA, VHDL & Co. ·Frank Stucke · ·12 Antworten

  • Thread

    FPGA Resource Verbrauch optimieren- bitte um Hilfe

    reset_n) IS BEGIN if reset_n = '0' then -- asyn reset_n yout_sat_reg <= (others=> '0'); Ki_Mantise_reg <= (others=> '0'); Kp_expopnet_reg <= (others=> '0'); Ki_exp_reg <= (others=> '0'); ysum_reg <= (others=> '0'); yi_alt <= (others=> '0'); start_delay <= (others=> '0'); op1_reg <= (others=> '0'); op2_reg <= (others=> '0'); -- ... elsif rising_edge(clk) then -- start: los! if ( start = '1' ) then -- Uebernahme gueltige Daten start_delay

    FPGA, VHDL & Co. ·Tomy · ·9 Antworten

  • Thread

    VHDL Timer & PWM

    ') then Counter <= (others => '0'); elsif(rising_edge(Clock_In)) then Counter <= Counter + 1; end if; case Prescaler is when "001" => Clock_Intern <= Counter(1);

    5); when "110" => Clock_Intern <= Counter(6); when "111" => Clock_Intern <= Counter(7); when others => Clock_Intern <= Counter(0); end case; end process;

    FPGA, VHDL & Co. ·Daniel K. · ·2 Antworten

  • Thread

    Verstädnisproblem bezüglich des Carry Bits

    1'; OV <= '1'; when "1ll" => C_Β <= '1'; OV <= '0'; when others => C_Β <= '0'; OV <= '0'; end case; else ZW : = VI - V2 - V3; TEMP := (ZW(WB - 1) , V2

    '; OV <= '1'; when "111" => C_B <= '1'; OV <= '0'; when others => C_B <= '0'; OV <= '0'; end case; end if; SUM <= To_bitvector(std_logic_vector(ZW(WB - 1 downto

    FPGA, VHDL & Co. ·Hans Peter · ·5 Antworten

  • Thread

    Mux als Tristate-Ersatz bläst das Design auf?

    ; when "11110" => d_out <= d_out_audio; when others => d_out <= (others => '-'); end case; end process MUX; [/vhdl] Soweit so gut. ISE 8.1 macht aber daraus (ich gucke

    Hingegen bei diesem Code hier: [vhdl] mux: process (fab,MCLK,count) begin case fab is when "00" => CO_CLK <= MCLK; when "01" => CO_CLK <= count(1); when "10" => CO_CLK <= count(0); when "11" => CO_CLK <= count(2); when others => null

    FPGA, VHDL & Co. ·Christian Peters · ·4 Antworten

  • Datei

    main.vhd

    when ADDR_MUX_HM2 ='1' else (others => 'Z'); -- Treiber Datenbus -- DATA <= DATA_BUF when ADDR(3) ='0' else (others => 'Z'); -- Schreiben process begin wait until falling_edge(NWE); if (NE1='1') then NULL

    in „Erzeugung von Tri - State Signalen?“ · FPGA, VHDL & Co. ·

  • Thread

    VHDL: Multiplexer mit generischer Anzahl zu muxender Busse?

    in 0 to (NumOfIORegisters-1) generate StatusBus <= StatusBits(Width*i+width-1 downto Width*i) when ChipSelect(i) = '1' else (others => 'Z'); end generate; [/vhdl] Nun muss ich andere FPGAs nehmen und die haben keine internen Tristate-Buffer. Wie baue ich einen generischen Multiplexer?

    Zeilen für NumOfIORegisters=3 und Width=8 hinschreibe: [vhdl] StatusBus <= StatusBits(7 downto 0) when ChipSelect(0) = '1' else (others => 'Z'); -- i=0 StatusBus <= StatusBits(15 downto 8) when ChipSelect(1) = '1' else (others => 'Z'); -- i=1 StatusBus <= StatusBits(23 downto 16) when ChipSelect(2)

    FPGA, VHDL & Co. ·Stefan Wimmer · ·11 Antworten

  • Thread

    Ansteuerung LCD Display(Spartan3E)

    <= data4; write_lcd <= '1'; when data4 => lcd_data <= x"74"; state_lcd <= lcdok; write_lcd <= '1'; when lcdok => null; when others => state_lcd <= lcdreset;

    <= setdata1; when others => state_lcd2 <= setdata1; end case; delay2 <= x"ff"; end if; end if; end if; end process; end Behavioral;

    FPGA, VHDL & Co. ·Christian · ·24 Antworten

  • Thread

    VHDL strukturbeschreibung

    " when "1101", --d "0000110" when "1110", --e "0001110" when others; --f with bin1 select sseg1 <= "1000000" when "0000", "1111001" when "0001",

    "0001110" when others; --f with bin2 select sseg2 <= "1000000" when "0000", "1111001" when "0001", "0100100" when "0010", "0110000" when "0011",

    FPGA, VHDL & Co. ·aero · ·1 Antworten

  • Thread

    Kurzer Peak (0ps) in Modelsim Simulation

    WHEN ERROR_IN = '0' ELSE (OTHERS => '1'); s_comparator(0) <= '1' WHEN s_check_signal_mod = CFG_IN_2 ELSE '0'; s_comparator(1) <= '1' WHEN s_check_signal_mod = CFG_IN_1 ELSE '0'; s_valid <= '

    Beitrag #3539275: > Welche Zustände meinst du? Z.B. den da: [vhdl] s_check_signal_mod <= ... (OTHERS => '1'); ... WHEN s_check_signal_mod = CFG_IN_2 ...; [/vhdl] Und den s_check_signal, der ja irgendwie mit Symbolen verheiratet wird, aber trotzdem nur ein Vektor ist... Wie gesagt, wir hatten

    FPGA, VHDL & Co. ·Thommy · ·9 Antworten

  • Thread

    Volladdierer, Probleme mir Simulation

    => Cout <= '0'; S <='1'; when "101" => Cout <= '1'; S <='0'; when "110" => Cout <= '1'; S <='0'; when others => Cout <= '1'; S <='1'; end case; end process Volladdierer; end Behavioral; [/

    => Cout <= '0'; S <='1'; when "101" => Cout <= '1'; S <='0'; when "110" => Cout <= '1'; S <='0'; when others => Cout <= '1'; S <='1'; end case; end process Volladdierer; [/vhdl] Das ist /funktional

    FPGA, VHDL & Co. ·chris · ·11 Antworten

  • Thread

    zwei Schieberegister

    bout1 <= longsr1(5); --weitere/andere Abgriffe bitte hier einfügen when "0001" => bout1 <= longsr1(10); when others => bout1 <= longsr1(9999); end case; longsr2<=longsr2(9998 downto 0) & bin2; case sel is when "0000" => bout2 <= longsr2(5); when "0001" => bout2 <= longsr2(10); when others => bout2 <= longsr2(9999); end case

    FPGA, VHDL & Co. ·Mathias H. · ·22 Antworten

  • Thread

    CPLD: XC95xx Problem mit Reset bei einem Latch

    Variable Mode : STD_LOGIC_VECTOR (3 downto 0); begin if RESET = '0' then Daten_MC <= (others => 'Z'); RDY_MC <= 'Z'; Daten_OUT <= (others => 'Z'); Adresse_OUT <= (others => 'Z'); RD_OUT <= 'Z'; WR_OUT <= 'Z'; Adresse <= (others => '0'

    (15 downto 8) <= Daten_MC; RDY_MC <= '1'; when others => Adresse <= Adresse; RDY_MC <= '0'; end case; end if; end process HAUPTPROZESS; end Verhalten; [/c]

    FPGA, VHDL & Co. ·netbandit · ·2 Antworten

  • Datei

    MCU.vhd

    "; FSMState <= Idle; BusWE <= '1'; RamCS <= '1'; BusAdress <= (Others => '0'); RamInitHappend <= '1'; RamCLKce <= '1'; end if; when Idle => State(3 downto 0) <= "0100"; case Sel is when "0000" => FSMState <= Idle; Bussy <= '0'; when "0001" => FSMState <= RamRead0; Bussy

    in „Problem mit der Ansteuerung von PSRAM“ · FPGA, VHDL & Co. ·

  • Datei

    MCU.vhd

    "; FSMState <= Idle; BusWE <= '1'; RamCS <= '1'; BusAdress <= (Others => '0'); RamInitHappend <= '1'; RamCLKce <= '1'; end if; when Idle => State(3 downto 0) <= "0100"; case Sel is when "0000" => FSMState <= Idle; Bussy <= '0'; when "0001" => FSMState <= RamRead0; Bussy

    in „Problem mit der Ansteuerung von PSRAM“ · FPGA, VHDL & Co. ·