Suchergebnisse für "when others"

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3880 Treffer für when others Suchergebnisse für "when others"

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  • Datei

    FCrypt.vhd

    generate_key : process (clock) variable n, m : byte; begin if rising_edge(clock) then case state is when zero => -- Initialisierungsphase -- Output-Ports ready <= '0'; done <= '0'; input <= '0'; output <= '0'; outkey_byte <= (others => '0'); -- Inkey write_enable_inkey <= '0'; address_inkey <= (others

    in „Tipps zur Fehlersuche gesucht“ · FPGA, VHDL & Co. ·

  • Thread

    Anfänger braucht Hilfe

    //Hier ist der Fehler FensterHeizstrahlerFehler(0) <= '1' WHEN "111", '1' WHEN "110", '1' WHEN "101", '1' WHEN "011", '1' WHEN "000", '0' WHEN OTHERS

    ' WHEN "100", '0' WHEN OTHERS; ELSE FensterHeizstrahlerFehler <= "000"; END IF; END PROCESS; END logic; [/vhdl]

    FPGA, VHDL & Co. ·Hannes Kr. · ·4 Antworten

  • Thread

    Xst:738 - HDL ADVISOR - 768 flip-flops were inferred for signal xxx.

    --------------------------- WITH rd_reg(i) SELECT reg_file_to_cpu <= dout_tmp(i) WHEN '1', (OTHERS => 'Z') WHEN OTHERS; END GENERATE output_regfile_gen; END GENERATE output_regfile_gen_condition; ---OUTPUT_REG_FILE_ANZAHL = 0-------

    µC----------------------- WITH rd_reg(i) SELECT cpu_databus <= input_reg_tmp(i) WHEN '1', (OTHERS => 'Z') WHEN OTHERS; END GENERATE input_regfile_gen; [/vhdl] Lothar Miller schrieb im Beitrag #1901273: > tomi schrieb: >> macht das dem Syntheser

    FPGA, VHDL & Co. ·tomi · ·12 Antworten

  • Datei

    SDRAM_Controller.vhd

    phase, then is used to trigger refreshes. constant startup_refresh_max : unsigned(13 downto 0) := (others => '1'); signal startup_refresh_count : unsigned(13 downto 0) := startup_refresh_max-to_unsigned(sdram_startup_cycles,14); -- logic to decide when to refresh signal pending_refresh : std_logic := '

    in „XC6SLX16 Spartan 6 Entwicklungsboard“ · FPGA, VHDL & Co. ·

  • Thread

    state machine, ein state mit verschiendenen Daten

    STATE, RESET) begin if RESET ='1' then STATE_next <= IDLE; else case STATE is when IDLE => STATE_next <= DATA_WRITE; when DATA_WRITE => if DATA_COUNTER = X"10" then STATE_next<=IDLE; else STATE_next <= DATA_WRITE; end case; end if; process(STATE, RESET) begin if RESET ='1' then ADDR<= (others => '0') ; DATA<= (others => '0') ; else case STATE is when IDLE => ADDR<= (others => '0') ; DATA<= (others => '0') ; when DATA_WRITE => ADDR<= ADDRESS;

    FPGA, VHDL & Co. ·chris · ·6 Antworten

  • Datei

    top.vhd

    allbit(38-send_databit_cnt); when 2 => MO_reg <= allbit(30-send_databit_cnt); when 3 => MO_reg <= allbit(22-send_databit_cnt); when others => end case; if send_databit_cnt < 6 then send_databit_cnt <= send_databit_cnt + 1; elsif send_databit_cnt

    in „INOUT wird bei der Synthese zu OUTPUT konvertiert“ · FPGA, VHDL & Co. ·

  • Thread

    Verbesserungsvorschläge gesucht

    when others => NULL; end case; end if; -- synchronous 8-bit read with read enable if (re = '1') then case address is when x"01" => do <= data(15 downto 8); when x"02" => do <= data(7 downto 0); when others => do <= (others=>'-'); end case; end if; end process; end std;[/vhdl] > bzw. 2 Schreibzyklen im Pico auf

    FPGA, VHDL & Co. ·Anfänger · ·29 Antworten

  • Datei

    IIR_Statemachine.vhd

    (others => '0'); nA1 <= (others => '0'); nA2 <= (others => '0'); nX <= (others => '0'); nY <= (others => '0'); oDone <= '0'; oIIR_TX <= (others => '0'); else case state is when idle => oDone <= '0'; if(iNewValue

    in „IIR Filter 2. Ordnung in FPGA implementieren“ · Digitale Signalverarbeitung / DSP / Machine Learning ·

  • PDF

    rts18160128fhc04-P16885-X01.pdf

    active. 18 RESB This is a reset signal input. Low active. D/C=”H”: Data. 19 DC D/C=”L”: Command. When connected to 8080-series MPU. WR pin. When RW =”L”: Write signal input. 20 RW When connected to 6800-series MPU. When RW =”H”: Read. When RW =”L”: Write. When connected to 8080-series MPU. RD pin.When

    in „RitDisplay RTS18160128FHC04 P16885 1,8" OLED Touch STM8“ · Mikrocontroller und Digitale Elektronik ·

  • Thread

    VHDL IF Problem

    AL<='0'; AR<='1'; AO<='0'; AU<='0'; ZVNEU<=ZU_B; when others => AL<='0'; AR<='0'; AO<='0'; AU<='0'; ZVNEU<=ZU_B; end case; [/vhdl] Sieht übersichtlicher aus und ergibt die selbe Funktion.

    AR<='0'; AO<='1'; AU<='0'; ZVNEU<=ZU_B; when "10" => AL<='0'; AR<='1'; AO<='0'; AU<='0'; ZVNEU<=ZU_B; when others => AL<='0'; AR<='0'; AO<='0'; AU<='0';

    FPGA, VHDL & Co. ·Wulf · ·24 Antworten

  • Thread

    Fehler in DDS?

    INCREMENT; ADDRESSING: process (LUT_IN, Delay_2) begin case Delay_2 is when "00" => DDS_OUT <= LUT_IN; when "01" => DDS_OUT <= LUT_IN; when "10" => DDS_OUT <= std_logic_vector(2**10 - unsigned (LUT_IN)); when "11" => DDS_OUT <= std_logic_vector(2**10 - unsigned (LUT_IN)); when others => null; end case; end process ADDRESSING; end; [/vhdl]

    FPGA, VHDL & Co. ·Max · ·5 Antworten

  • Thread

    [vhdl] Kürze schreibweise für eine State machine

    "0000000000010000" => foo_out <= "0101"; when "0000000000100000" => foo_out <= "0110"; when "0000000001000000" => foo_out <= "0111"; when "0000000010000000" => foo_out <= "1000"; when "0000000100000000" => foo_out <= "1001"; when

    "0100000000000000" => foo_out <= "1111"; when "1000000000000000" => foo_out <= "0001"; when "0000000000000000" => foo_out <= "0000"; when others => foo_out <= "0000"; end case; [/vhdl] dann machst halt satt foo_out zu setzen deine Anweisungen

    FPGA, VHDL & Co. ·Karsten Seibt · ·8 Antworten

  • Datei

    Main.vhd

    ; end if; else FSM_F_ZUSTAND <= FSM_RESET; end if; when FSM_WAIT_PRESENCE => READ_EN <= '1'; -- Read Slot auslösen if INPUT_BUFFER /= "1111111111111111" then -- prüfen, ob eine Null gelesen wurde FSM_F_ZUSTAND <= FSM_SKIP_ROM; --INPUT_BUFFER <= (others =

    in „[Fehlersuche] Ansteuerung eines 1-Wire Sensors“ · FPGA, VHDL & Co. ·

  • Thread

    Asynchronous load of non constant data for is not supported

    ADC_A_nOE <= '0'; ADC_A_CLK <= '0'; ADC_Channel_A_NewData <= '0'; ADC_Channel_A <= (others => '0'); ADC_Channel_A_Overflow <= '0'; case ADC_CurrentState_A is when S_SLEEP => ADC_A_SHDN <= '1'; ADC_A_nOE <= '1';

    32MHz-Takt im FPGA mit einer PLL o.ä. und du bekommst damit automatisch die doppelte Datenrate. >>> OTHERS clause is not synthesized Das kommt von: when others => ADC_NextState_A <= S_SLEEP; Und das ist unnötig, weil ja vorher schon alle Zustände von ADC_STATE verwendet sind.

    FPGA, VHDL & Co. ·Steffen · ·4 Antworten

  • Datei

    top.vhdl

    to_unsigned(x mod 64)); ramp2 := std_logic_vector(to_unsigned((XMAX - x) mod 64)); case section is when 0|3|4|6|7|10|11|13|14 => r <= ramp1; when 8|9|12 => r <= (others => '1'); when others => r <= (others => '0'); end case; case section is when 1|3|5|6|8|10|12 => g <= ramp1; when 13 => g <= ramp2; when 7|9|11 => g <= (others => '1'); when others => g <= (others => '0'); end case; case section is when 2|4|5|6|9|11|12 => b <= ramp1; when 14 => b <= ramp2; when 7|8|10 => b <= (others => '1'); when others => b <= (others =

    in „Anschluß TFT-LCD-Modul SHARP LQ092B5DW01 Pollin“ · Mikrocontroller und Digitale Elektronik ·

  • Thread

    Datentyp in VHDL

    "; when 6 => display <= "1111110"; when 7 => display <= "0100011"; when 8 => display <= "1111111"; when 9 => display <= "1110111"; when others => display <= "0000000"; end case; end

    when x"E" => res := "1001111"; when x"F" => res := "1000111"; when others => res := "1111111"; -- nur fuer Simulation end case; return res; end; Der Aufruf könnte

    FPGA, VHDL & Co. ·Tobias Danz · ·8 Antworten

  • Thread

    Probleme mit der Erstellung eines Automaten

    WHEN OTHERS => reg_WR <= 'X'; reg_RD <= 'X'; report "Reach undefined state"; END CASE; END IF; END PROCESS; END BEHAVIOR

    std_logic_vector(7 downto 0); : architecture machwas .... : datain <= data; data <= dataout when write='1' else (others=>'Z'); -- IO-Treiber umschalten end machwas; [/vhdl]

    FPGA, VHDL & Co. ·Lst · ·6 Antworten

  • Datei

    IIR.vhd

    (others => '0'); nA1 <= (others => '0'); nA2 <= (others => '0'); nX <= (others => '0'); oDone <= '0'; oIIR_TX <= (others => '0'); else case state is when idle => oDone <= '0'; if(iNewValue = '1') then -- If

    in „IIR Filter 2. Ordnung in FPGA implementieren“ · Digitale Signalverarbeitung / DSP / Machine Learning ·

  • Datei

    CONTROLLER.vhd

    nach dem nächsten Takt abgeschaltet PORT0_MODUS <= UNUSED; -- und Port 0 wird freigegeben end if; when Z2 => -- Zustand 2 SM2 <= Z1; PORT0_E <= '0'; -- Datenausgabe an Port 0 abschalten PORT0_DO <= (others => '0'); -- Port 0 Datenausgabe löschen when others => -- anderer Zustand SM2 <= Z1; end case;

    in „eigenartige Post-Fit Simulation“ · FPGA, VHDL & Co. ·

  • Datei

    IIR.vhd

    (others => '0'); nA1 <= (others => '0'); nA2 <= (others => '0'); nX <= (others => '0'); nY <= (others => '0'); oDone <= '0'; oIIR_TX <= (others => '0'); else case state is when idle => oDone <= '0'; if(iNewValue

    in „IIR Filter 2. Ordnung in FPGA implementieren“ · Digitale Signalverarbeitung / DSP / Machine Learning ·

  • Thread

    synchronzähler - codefehler (vhdl)

    when "1001" => d:="1000"; when others => d:="0000"; end case; y<=c; end process P1; end Behavioral;

    "1011" => d:="1001"; when "1001" => d:="1000"; when others => d:="0000"; end case; end process P1; y <= d; end Behavioral; 1.) Die Formatierung ist wichtig um Fehler zu erkenen. 2.) Man braucht für einen

    FPGA, VHDL & Co. ·Stefan Helmert · ·15 Antworten

  • Thread

    Couldn't implement registers Prescaler problem

    sehe ich das :) [VHDL] PROCESS(CLK_250, PRSCL,CLK_ADC_SIG)---CLK FOR ADC BEGIN CASE PRSCL IS WHEN 1 => ----NO PRESCALER CLK_ADC<=CLK_250;--- IF NO PRESCLAER THEN ASSIGN CLK TO ADC_CLK WHEN OTHERS => ---ELSE USE PRESCALER IF(CLK_250'EVENT AND CLK_250='1')THEN ADC_PRSC<=ADC_PRSC+1;

    schließlich hat er mehr Erfahrung als ich:) [vhdl] WITH CLK_DIV SELECT CLK_ADC <= CLK_250 WHEN '0', CLK_ADC_SIG WHEN OTHERS; PROCESS(CLK_250, PRSCL)---CLCK FOR ADC BEGIN IF(CLK_250='1' AND CLK_250'EVENT)THEN CASE PRSCL IS WHEN 0 => CLK_DIV<='0';-

    FPGA, VHDL & Co. ·GS · ·6 Antworten

  • Datei

    Main.vhd

    ; end if; else FSM_F_ZUSTAND <= FSM_RESET; end if; when FSM_WAIT_PRESENCE => READ_EN <= '1'; -- Read Slot auslösen if INPUT_BUFFER /= "1111111111111111" then -- prüfen, ob eine Null gelesen wurde FSM_F_ZUSTAND <= FSM_SKIP_ROM; --INPUT_BUFFER <= (others =

    in „[Fehlersuche] Ansteuerung eines 1-Wire Sensors“ · FPGA, VHDL & Co. ·

  • Datei

    simple_uart.vhd

    shiftTx, stopTx if rising_edge(clk) then if rst = '0' then -- synchronous active-low reset TxReg <= (others => '1'); TxState <= idle; TxBusy <= '0'; one_start <= '0'; -- eventuell Datenregister einfuehren else TxBusy <= '1'; -- always busy except when explicitly not TxD <= TxReg(0); case TxState is when

    in „UART Receiver oft Parity Error“ · FPGA, VHDL & Co. ·

  • Datei

    IIR.vhd

    ); help4 <= (others => '0'); else case state is when idle => oDone <= '0'; if(iNewValue = '1') then -- If new signal arrives state <= mul; -- Change state to multiply nX(INPUT_WIDTH-1 downto 0) <= signed(iIIR_RX); --

    in „IIR Filter 2. Ordnung in FPGA implementieren“ · Digitale Signalverarbeitung / DSP / Machine Learning ·

  • Datei

    vga.vhd

    fifo_in_full or switchpending); process(clk,reset) begin if (reset = '1') then doublebuffertreshold <= (others => '0'); clip_x_min <= (others=>'0'); clip_x_max <= (others=>'1'); clip_y_min <= (others=>'0'); clip_y_max <= (others=>'1'); elsif (clk'event and clk='1') then if (wr='1') then if addr = X"1000000"

    in „SRAM auf DE2 Board“ · FPGA, VHDL & Co. ·

  • Thread

    VHDL - Problem

    Probiere mal eine defaultzuweisung "when others" wie unten angegeben. Dann sollte es funktionieren. Ansonsten kann ich absolut keine Fehler finden. EINSTINT <= '0' when EINSTELL = "0000" else '1' when EINSTELL = "0001" else '1' when EINSTELL = "0010" else '1' when EINSTELL = "0100" else '1' when EINSTELL = "1000" else '0' when others ;

    FPGA, VHDL & Co. ·Beeblebrox · ·3 Antworten

  • Datei

    PS2_Keyboard_Ctrl.vhd

    if; when WAIT_BYTE1 => Input_Buffer <= (others => '1'); -- PS/2 Startbedingung erkannt if((PS2_DataSR(1) = '0') and (PS2_ClockSR(1) = '1')) then PS2_State <= RECEIVE_BYTE1; end if; when RECEIVE_BYTE1 => -- Startbit

    in „PS/2 im FPGA“ · FPGA, VHDL & Co. ·

  • Thread

    Latch statt Multiplexer?

    INPUTMux:process(INPUT_MODE,INPUT_ALU,INPUT_BYP) begin case INPUT_MODE is when "00" => input_int <= INPUT_ALU; when "01" => input_int <= INPUT_BYP; when others => input_int <= INPUT_ALU; end case; end process; OUTPUTMux:process(OUTPUT_MODE,input_int,INPUT_ALU,INPUT_BYP,INPUT_MODE) begin case OUTPUT_MODE is when "00" => OUTPUT_REG <= input_int; when "01" => OUTPUT_DIRECT <= input_int; when others => OUTPUT_REG <= input_int; end case; end process;

    FPGA, VHDL & Co. ·TM · ·3 Antworten

  • Thread

    parametrisierbarer Binärzäher

    Verschärft kann man dann ans Ende der Liste noch ein /others/ einbringen: [vhdl] signal <= (Bitnummer/Range=>Wert1, Bitnummer/Range=>Wert2, ..., others=>Wert3); [/vhdl]

    schon angesprochen ersetzen durch: [vhdl] constant count_max : std_logic_vector (n-1 downto 0) := (others=>'1');[/vhdl]

    FPGA, VHDL & Co. ·Chris · ·14 Antworten

  • Thread

    VHDL - Vertauschte Endianness

    architecture FOO_beh of FOO is signal SpiReg : std_logic_vector (15 downto 0):=(others=>'0'); signal bar0 : std_logic_vector (1 downto 0):=(others=>'0'); p40: process (SpiClk) begin if rising_edge (SpiClk) then if nSpiCs='0' then SpiReg(

    downto 0); pBAR0: process (bar0, fooIn0, fooIn1, fooIn2, fooIn3) begin case bar0 is when "00" => foo0Out<=fooIn0; when "01" => foo0Out<=fooIn1; when "10" => foo0Out<=fooIn2; when "11" => foo0Out<=fooIn3; when others => foo0Out<='0'; end case; end

    FPGA, VHDL & Co. ·M. Vollmer · ·12 Antworten

  • Thread

    FlipFlops für Ausgänge einer Entity

    if Reset = '1' then i <= 0; elsif rising_edge(clk) then case i is when 0 => ValOut <= b"1011"; when 1 => ValOut <= b"0101"; when 2 => ValOut <= b"1101"; when others => ValOut <= (others => 'X'); end case; if i = 3 then

    else i <= i + 1; end if; end if; end process; ValOut <= b"1011" when i=0 else b"0101" when i=1 else b"1101" when i=2 else (others => 'X'); end Behavioral; [/vhdl] Auch daran solltest du auch noch arbeiten: [vhdl] signal

    FPGA, VHDL & Co. ·Max · ·4 Antworten

  • Datei

    BlinkLED.vhd

    WHEN "1100" => asci := x"43"; --C WHEN "1101" => asci := x"44"; --D WHEN "1110" => asci := x"45"; --E WHEN "1111" => asci := x"46"; --F WHEN OTHERS => asci := x"21"; --! END CASE; return asci; end ASCII;

    in „Taschenrechner in VHDL“ · FPGA, VHDL & Co. ·

  • Thread

    EPJ15 S. 7: PWM mit FPGA

    <="1111111110"; when 1600 => led_vector <="1111111111"; when others => led_vector <= "0000000000"; end case; if reset = '0' then pwm_out <= '0'; else if

    <="1111111110"; when 1600 => led_vector <="1111111111"; when others => led_vector <= "0000000000"; end case; if (count1 < (PWM_freq - PWM_HIGH)) then pwm_out <= '0';

    FPGA, VHDL & Co. ·Christian Kähler · ·34 Antworten

  • Thread

    Eigenen Code sauber in PLB Slave Template einbinden

    Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Reset = '1' then slv_reg0 <= (others => '0'); slv_reg1 <= (others => '0'); --slv_reg2 <= (others => '0'); else case slv_reg_write_sel is when "100" => for byte_index in 0 to (C_SLV_DWIDTH

    (byte_index*8 to byte_index*8+7); -- end if; -- end loop; when others => null; end case; end if; end if; end process SLAVE_REG_WRITE_PROC; [/vhdl] In diesem Prozess werden die definierten Register ja vom Bus beschrieben. Um zu verhindern

    FPGA, VHDL & Co. ·A. M. · ·5 Antworten

  • Thread

    Alles wird wegoptimiert

    --------------------------------------------------------------------- case fsm_cur is when SS_RST => fsm_next <= SS_INI; when SS_INI => fsm_next <= SS_ACTIVE; when SS_ACTIVE => ena <= '1'; when others => fsm_next <= SS_RST; end

    after -- und bei der Synthese durch die FSM versteckt when others => fsm_next <= SS_RST; end case; end fsm; -- Sequential: Common register block ---------------------------------------------------------------------- seq : process

    FPGA, VHDL & Co. ·Jonny · ·31 Antworten

  • Datei

    CCD.vhd

    <='0'; WHEN GETY=> IF(INIT='1')then validin<='1'; end if; Comp_Y<=BT656_DATA; IF(STATE_FLAG='1')THEN STATE<=GETCR; ELSE STATE<=GETCB; END IF; WHEN OTHERS=> LEDR(5)<='1'; END CASE; ELSE validin<='0'; STATE_FLAG<

    in „Timing Requierement not met.Das System funktioniert nicht“ · FPGA, VHDL & Co. ·

  • Datei

    ALU.vhd

    0'; end if; when others => NULL; end case; --Pipeline Stage 3 case SelectPipe(2) is when "0000" => YPipe(2)(23 downto 16) <= (others => '0'); CarryPipe(2) <= '0'; when "0001" => YPipe(2)(23 downto 16) <= OaPipe(2)(23

    in „Problem mit "Eigenbau" Pipeline ALU“ · FPGA, VHDL & Co. ·

  • Thread

    CORDIC in VHDL

    sintemp(9) & sintemp(9 DOWNTO 7)); WHEN OTHERS => data := "000000000000"; I_shift:= costemp; Q_shift:= sintemp; END CASE;

    sintemp(9) & sintemp(9 DOWNTO 7)); WHEN OTHERS => data := "000000000000"; I_shift:= costemp; Q_shift:= sintemp; END CASE;

    FPGA, VHDL & Co. ·Benedict · ·35 Antworten

  • Datei

    lcddriver.vhd

    x"A" => fifo_data <= x"41"; when x"B" => fifo_data <= x"42"; when x"C" => fifo_data <= x"43"; when x"D" => fifo_data <= x"44"; when x"E" => fifo_data <= x"45"; when x"F" => fifo_data <= x"46"; when others => fifo_data <= x"58"; --

    in „LC-Display ansteuern in VHDL“ · FPGA, VHDL & Co. ·

  • Thread

    Frage zum Sparten 3A

    distribution process(clk) begin if clk='1' and clk'event then case sel is when "00" => toggle <= '0'; when "01" => toggle <= not toggle; when "10" => if cnt(15)='1' then toggle <= not toggle; else toggle<='0'; end if; when others => null; end case; drive_ar<=(others=>toggle); end if; end process; gnd<=(others=>'0'); mod_out<=cnt(15); end Behavioral; [/vhdl] [vhdl] library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

    FPGA, VHDL & Co. ·Peter Falk · ·36 Antworten

  • Thread

    std_logic zu std_logic_vector

    [vhdl] s_exa_slv <= (others => s_exa_sl); [/vhdl]

    IDATA_P(PLOOP+1) <= IDATA_P(PLOOP); end loop; PD_OUT_N <= (others => IDATA_N(63)); for NLOOP in 62 downto 0 loop IDATA_N(NLOOP+1) <= IDATA_N(NLOOP); end loop; when others => null; end case; end

    FPGA, VHDL & Co. ·Mark W. · ·12 Antworten

  • Datei

    Uhr.vhd

    is array(1 downto 0) of ziffer; signal sekunden_neu, minuten_neu, stunden_neu : doppel_ziffer := (others => (others => '0')); signal sekunden_alt, minuten_alt : doppel_ziffer := (others => (others => '0')); signal zaehler : integer range 0 to teiler; begin -- Teilt die Taktfrequenz von 50 MHz durch 50.000.000

    in „Ansteuerung LCD Anzeige Spartan“ · FPGA, VHDL & Co. ·

  • Datei

    IIR_Statemachine.vhd

    (others => '0'); nA1 <= (others => '0'); nA2 <= (others => '0'); nX <= (others => '0'); oDone <= '0'; oIIR_TX <= (others => '0'); else case state is when idle => oDone <= '0'; if(iNewValue = '1') then -- If

    in „IIR Filter 2. Ordnung in FPGA implementieren“ · Digitale Signalverarbeitung / DSP / Machine Learning ·

  • Datei

    IIR_Statemachine.vhd

    (others => '0'); nA1 <= (others => '0'); nA2 <= (others => '0'); nX <= (others => '0'); oDone <= '0'; oIIR_TX <= (others => '0'); else case state is when idle => oDone <= '0'; if(iNewValue = '1') then -- If

    in „IIR Filter 2. Ordnung in FPGA implementieren“ · Digitale Signalverarbeitung / DSP / Machine Learning ·

  • PDF

    ALSE_UART_us.pdf

    ; when "111" => Divisor <= 767; -- 1.200 end if; when others => Divisor <= 7; -- n.u. end process; end case; end if; end process; -- ------------------------------ -- Rx Sampling Clock Generation -- ------

    in „RS232-Empfänger mit PLD“ · FPGA, VHDL & Co. ·

  • Thread

    Ampelschaltung - Probleme bei der Synchronisation

    ignoriert, weil es ja keinen weiteren Zustand mehr gibt! Fazit: [vhdl] Lights <= "100" when (State = gruen) else "110" when (State = rotgelb) else "001" when (State = rot) else "010" ; -- State = gelb [/vhdl] Das ist so ähnlich, wie die /when others/ Sache: http://www.lothar-miller.de/s9y/categories/25-when-others Christian Klingler schrieb im Beitrag #2850173: > if rising_edge(clk) then > if counter = 7999999 then > New_Clock <= not New_Clock; > counter := 0; > else > counter

    FPGA, VHDL & Co. ·Christian Klingler · ·15 Antworten

  • Thread

    Register in VHDL effizien implementieren?

    Daten ausgeben wenn dieses Modul adressiert INT_D_OUT(31 downto 0) <= INT_D_OUT_sig(31 downto 0) when INT_CYCLE_access = '1' else (others => 'Z'); ------------------------------------------------------- end COUNTERRegister_arch; [/vhdl] Das Tristate Problem ist nun aber trotzdem noch nicht gelöst

    INT_D_out1 or INT_D_out2 or INT_D_out3 ... [/c] Und in der Sub-Einheit: [c]IND_D_out1 <= Reg_Out1 when ((CS1 = '1') and (read_access = '1')) else (others => '0');[/c] Gruß Bernd

    FPGA, VHDL & Co. ·Martin Kohler · ·10 Antworten

  • Datei

    cordic.vhd

    order to support clamping d.t. an add'l offset signal sintemp, costemp : signed (16 downto 0) := (others => '0'); -- Current angle, should converge to 'phase' when iterating signal angle : signed (14 downto 0) := (others => '0'); -- Counter for our state machine (step thru all pre-defined angles (arctan

    in „CORDIC in VHDL“ · FPGA, VHDL & Co. ·

  • Thread

    Case nur mit Takt möglich?

    "1001" => led_o <= "1111011"; -- 9 WHEN OTHERS => led_o <= "1111110"; -- 0 END CASE; WAIT; END PROCESS; END seg7_a;[/vhdl] Wenn ich eine Simulation starte, kommt egal bei welcher BCD Kombination immer der letzte Wert (hier WHEN OTHERS => led_o <= "1111110"; -- 0). Ist so ein Case Konstrukt nur mit einem Takt möglich? Oder warum wird immer der letzte Wert genommen?

    FPGA, VHDL & Co. ·Markus X. · ·7 Antworten