Suchergebnisse für "when others"

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3880 Treffer für when others Suchergebnisse für "when others"

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  • Datei

    spi_struct.h

    state.*/ uint32_t reserved24 : 5; /*reserved*/ uint32_t ck_idle_edge : 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.*/ uint32_t cs_keep_active : 1; /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/ uint32_t quad_din_pin_swap

    in „C > Struct > Pointer - Adresszuweisung“ · Mikrocontroller und Digitale Elektronik ·

  • Datei

    AC1_2011.vhd

    PIO PIOM1 <= M1 and Reset ; -- Verknüpfung -- Signal IO1x erzeugen IO1x <= IORQ when ADR(7 downto 3) = "00010" and WR = '0' else '1' ; -- Modul 1 Latch auf IO-PORT 14H IO14(3 downto 0) <= (others => '0') when (Reset = '0') else DB(3 downto 0) -- Latch laden when (IO1x = '0' and ADR(2 downto 0)="100") else IO14(3 downto 0) ; -- Modul 3 Latch auf IO-PORT 15H IO15 <= (others => '0') when (Reset = '0') else DB -- Latch laden when (ADR(7 downto 0) = x"15" AND IORQ = '0' AND WR = '0') else IO15 ; -- Modul 1 IO16H Register.. RAM ab 0..FFFH IO16 <= '0' when (Reset = '0') else

    in „Fitterproblem“ · FPGA, VHDL & Co. ·

  • Datei

    FP_Setup_Type.vhd

    , x"ff80" when others; with to_integer(unsigned(SRate)) select DP_SR <= 3 when 13 | 17, 4 when others; NumVal32 <= "000" & std_logic_vector(unsigned(NChannels) + 1) when unsigned(MuxCount) < 4 else "000" & std_logic_vector

    in „Nach type-Dekaration ganz woanders Sysntaxfehler?“ · FPGA, VHDL & Co. ·

  • Thread

    Problem: Latches oder unkorrektes Verhalten

    ALU_OP : process (A_reg, B_reg, u_instruction) begin CASE u_instruction is when op_lda => alu_out <= A_reg; when op_ldb => alu_out <= A_reg; when op_add => ALU_out <= (A_reg + B_reg); ------------------------------------------

    ---------------------------------------------------------------------- when others => ALU_Out <= (others => '0'); end CASE; end process ALU_OP; [/vhdl] Die Flags kommen da nicht rein. Z und C kann man einfach so dekodieren [vhdl] Z <=0 when alu_out =0 else

    FPGA, VHDL & Co. ·Screamapilla · ·23 Antworten

  • Datei

    TSBUF.vhd

    schnipsel OF blafasel IS SIGNAL OUT_EN : BIT := '0'; SIGNAL OUT_DATA : STD_LOGIC_VECTOR( 7 DOWNTO 0) := (OTHERS => '0'); SIGNAL IN_DATA : STD_LOGIC_VECTOR( 7 DOWNTO 0) := (OTHERS => '0'); SIGNAL CFG_DATA : STD_LOGIC_VECTOR( 7 DOWNTO 0) := (OTHERS => '0'); SIGNAL X_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS

    in „VHDL-Tristatebuffer will nicht“ · FPGA, VHDL & Co. ·

  • Thread

    wWarum wird nicht geschoben

    0):= (others => '0'); begin Clock_LR: Vorwzhl Port map ( Clk => CLK, Rst => RESET, CTL_DOTO => CTL_TODO, ZClk => CLK_LR ); Process (CLK, RESET) begin

    (CLK)) then case state is when idle => byte_count <= 0; bit_count <= 0; trigger_count <= 0; value_count <= 0;

    FPGA, VHDL & Co. ·A. ZANAM · ·5 Antworten

  • Thread

    FIFO Implementierung in BlockRAM

    ram_type is array (255 downto 0) of STD_LOGIC_VECTOR(15 downto 0); signal RAM : ram_type := (others => (others => '0')); [/vhdl] Gibt es evtl. noch Rückmeldungen zum konzeptionellen Aufbau meines FIFOs? Oder hat gar einer einen VHDL Beispielcode? Über Sinn oder Unsinn möchte ich mich nicht

    if reset = '1' then -- sync reset addr_rd <= (others =>'0'); addr_wr <= (others =>'0'); underflow <= '0'; overflow <= '0'; else -- process inputs

    FPGA, VHDL & Co. ·Martin Kohler · ·31 Antworten

  • Datei

    74185.vhd

    1' WHEN 28, -- '0' WHEN OTHERS; -- WITH conv_input SELECT -- bcd_o(3) <= -- '1' WHEN 4, '1' WHEN 9, '1' WHEN 14, '1' WHEN 19, -- '1' WHEN 24, '1' WHEN 29, -- '0' WHEN OTHERS; -- WITH conv_input SELECT -- bcd_o

    in „VHDL Design für den IC 74185“ · FPGA, VHDL & Co. ·

  • Datei

    MultiplierNEU.vhd

    signal SUM1,SUM2,SUM3 : bit_vector ( 8 downto 0 ); begin PP1: process (A,B,H) begin case B(0) is when '1' => H(0)<=A(0); H(1)<=A(1); H(2)<=A(2); H(3)<=A(3); when others => H <=(others=>'0'); end case; end process PP1; PP2: process(A,B,I) begin case B(1) is when '1' => => I(0) <= '0'; => I(1) <=A(0);

    in „Case-When Fehlermeldung brauche Hilfe“ · FPGA, VHDL & Co. ·

  • Datei

    npl30d.vhd

    and (P26 = '0')) then mmc_ireg <= '0'; elsif PLCLK1 = '1' and PLCLK1'event then case state is when state_wait_start => mmc_coreg <= '0'; mmc_doreg <= '0'; mmc_creg <= (others=>'0'); mmc_out <= mmc_mosi_reg; if (start = '1') then state <= state_clock_low; end if; when state_clock_low => mmc_coreg

    in „Probleme bei der Umstellung von Verilog nach VHDL“ · FPGA, VHDL & Co. ·

  • Datei

    i2c_slave.vhd

    read_process: process(clock, reset) begin if reset = '1' then read_state <= idle; input_shift <= (others => '0'); else if rising_edge(clock) then case read_state is when idle => if read_byte then input_shift_count <= 7; read_state <= read_bit; end if; if read_ack then input_shift_count <= 0; read_state

    in „i2c slave zum testen“ · FPGA, VHDL & Co. ·

  • Thread

    VHDL: Zufallswerte für die Initialisierung erzeugen

    array_t is array (0 to 2**data_select'length) of integer; constant const_array : array_t := (others => random); begin -- Damit nicht alles wegoptimiert wird data_out <= to_unsigned(const_array(to_integer(data_select)), data_out'length); end architecture; [/vhdl]

    Just like other pseudo-random number generators, uniform will generate the same sequence of numbers when called with the same initial seed values. Because of this behavior, you can rerun the testbench and get the same result when using the same seed values." Da in den hier gezeigten Codes die Seeds fest

    FPGA, VHDL & Co. ·Florian · ·15 Antworten

  • Datei

    SECU.vhd

    ; when WaitBussyWait => FSMState <= WaitBussy; when NOP => BusAdress <= (Others => '0'); BusConf <= (Others => '0'); BusFlags <= (Others => '0'); BusDataDirekt <= (Others => '0'); NOPCounter <= NOPCounter

    in „Problem mit dem Laden eines Counters“ · FPGA, VHDL & Co. ·

  • Thread

    NAND-Flash Reader mit FTDI-USB

    einem FTDI schon mal (möglichst einfach) gelöst? Knulli case FIFOWriteStatus is when FIFO_WR_IDLE => if STA = '0' then FIFOWriteStatus <= FIFO_WAIT_TXE; FIFO_Data <= (others => 'Z'); ByteCNT <= (others => '0'); end if; when FIFO_WAIT_TXE => if TXE = '0' then FIFOWriteStatus <= FIFO_WR_DATA; end

    FPGA, VHDL & Co. ·Knut E. · ·7 Antworten

  • Datei

    mt48lc32m8a2.vhd

    " Bank-3 "; WHEN others => ASSERT false REPORT InstancePath & partID & ": Could not decode bank" & " selection - results may be incorrect." SEVERITY SeverityMode; END CASE; END IF; -- The Big State Machine IF (rising_edge

    in „Problem mit vital.timing und vital.primitives“ · FPGA, VHDL & Co. ·

  • Thread

    Timing Simulation Quartus+ModelSim mit Testbench - Signale gehen in unbesimmten Zusand

    reset) begin if reset = '1' then currentstate <= resetSTATE; frame_addr <= (others => '0'); failure <= "000"; elsif rising_edge(clk) then case currentstate is when resetSTATE => -- alle Signales werden resettet-spar ich an der Stelle

    <= '0'; currentCYCO <= execCYCO; end if; when execCYCO => rst_n_cnt <= '1'; if (ctrl_in(2)) = '0' then currentCYCO <= idleCYCO; end if; when others => end case;

    FPGA, VHDL & Co. ·Dustin F. · ·15 Antworten

  • Datei

    idct.vhd

    process idct_read_p; data_p: process(clk,reset) --(1 clk) begin if(reset='1') then data_a_reg(0)<=(others => '0'); data_a_reg(1)<=(others => '0'); data_a_reg(2)<=(others => '0'); data_a_reg(3)<=(others => '0'); data_a_reg(4)<=(others => '0'); data_a_reg(5)<=(others => '0'); data_a_reg(6)<=(others => '0

    in „Simulationsproblem bei XOR-Verknüpfung“ · FPGA, VHDL & Co. ·

  • Thread

    Fehler bei Synthese

    COMB:process(zustand,counter) begin case zustand is when S0 => folge<=S1; a<='0'; when S1 => if counter< 7 then folge<=S0; a<='0'; else folge<=S2; a<='0'; end if; when S2 => folge<=S0; a<='1'; end case; end process COMB; [/vhdl] MFG

    FPGA, VHDL & Co. ·vhdler · ·6 Antworten

  • Thread

    Using the 7-segment Displays/ 7 Segment Anzeige

    " => a <= '1'; b <= '1'; c <= '1'; d <= '1'; e <= '1'; f <= '1'; g <= '1'; when "1001" => a <= '1'; b <= '1'; c <= '1'; d <= '1'; e <= '0'; f <= '1'; g <= '1'; when others => a <= '0'; b <= '0'; c <= '0'; d <= '0'; e <= '0'; f <= '0'; g <= '1'; END case;

    " => a <= '1'; b <= '1'; c <= '1'; d <= '1'; e <= '1'; f <= '1'; g <= '1'; when "1001" => a <= '1'; b <= '1'; c <= '1'; d <= '1'; e <= '0'; f <= '1'; g <= '1'; when others => a <= '0'; b <= '0'; c <= '0'; d <= '0'; e <= '0'; f <= '0'; g <= '1'; END case;

    FPGA, VHDL & Co. ·Manah · ·17 Antworten

  • Datei

    74185.vhd

    1' WHEN 28, -- '0' WHEN OTHERS; -- WITH conv_input SELECT -- bcd_o(3) <= -- '1' WHEN 4, '1' WHEN 9, '1' WHEN 14, '1' WHEN 19, -- '1' WHEN 24, '1' WHEN 29, -- '0' WHEN OTHERS; -- WITH conv_input SELECT -- bcd_o

    in „VHDL Design für den IC 74185“ · FPGA, VHDL & Co. ·

  • Datei

    TSBUF.vhd

    RD Signal ... ... signal OUT_EN : bit:='0'; signal OUT_DATA : STD_ULOGIC_VECTOR(7 downto 0) := (others => '0'); signal IN_DATA : STD_ULOGIC_VECTOR(7 downto 0) := (others => '0'); signal CFG_DATA : STD_ULOGIC_VECTOR(7 downto 0) := (others => '0'); signal X_DATA : STD_ULOGIC_VECTOR(11 downto 0) := (others

    in „VHDL-Tristatebuffer will nicht“ · FPGA, VHDL & Co. ·

  • Thread

    Komplexe Pipeline mit AXI-Stream: Ready-Signal kombinatorisch?

    -- reset definition constant REG_RESET : reg_t := ( fsm => S_0, set0_data => (others => 'U'), set1_data => (others => 'U') ); -- functions function mult(a, b : std_ulogic_vector(DATA_WIDTH - 1 downto 0)) return std_ulogic_vector is begin return std_ulogic_vector

    when S_0 => a_ready_o <= b_valid_i; b_ready_o <= a_valid_i; c_data_o <= (others => 'U'); c_valid_o <= '0'; when S_1 => a_ready_o <= b_valid_i;

    FPGA, VHDL & Co. ·dzopf · ·6 Antworten

  • Thread

    Hyperram ohne nios 2 ?

    SDRAM1; architecture Behavioral of SDRAM1 is signal x : std_logic_vector (3 downto 0) := (others=>'0'); type state_type is (state_decision, state_read, state_write); signal state : state_type; --für Ram signal myAddress : std_logic_vector (9 downto 0) := (others=>'0'); signal

    ; when others => state <= state_decision; end case; end if; end process; leds <= not x; -- Signal x an LEDs ausgeben end Behavioral; [/

    FPGA, VHDL & Co. ·FPGA Neuling · ·10 Antworten

  • Datei

    Speed.vhd

    <= INIT; when V1 => IMP4 <= '1'; --DIR <= '1'; F_ZUSTAND <= V10; when V2 => IMP4 <= '1'; --DIR <= '1'; F_ZUSTAND <= V20; when V3 => IMP4 <= '1'; --DIR <= '1'; F_ZUSTAND <= V30; when V4 => IMP4 <= '1'; --DIR <= '1

    in „[VHDL] Komponenten Einbinden und wegoptimieren von Signalen verhindern“ · FPGA, VHDL & Co. ·

  • Datei

    idt70V3319.vhd

    TAP_state = Select_DR_Scan THEN BSR_READ <= false; ELSIF TAP_state = Shift_DR THEN CASE instruction IS WHEN idcode => TDO_zd := IDreg(0); WHEN bypass => TDO_zd := bpr; WHEN extest => TDO_zd := bsr(0); WHEN sample_preload => TDO_zd := bsr(0); WHEN others => null; END CASE; ELSIF TAP_state = Exit1_DR THEN TDO_zd

    in „Fehler bei RAM-Simulation“ · FPGA, VHDL & Co. ·

  • Datei

    TEM_uni_5_adc_stream.vhd

    ADC_data_ready <= AD7356_56_data_ready; when others => ADC_data <= fifo_counter; ADC_data_ready <= fifo_counter_ready; end case; --ADC_data <= fifo_counter; ADC_data_ready <= fifo_counter_ready; end process; --------- write to FIFO -----------

    in „Wie Clockdomain crossing für FT232H, wie debuggen?“ · FPGA, VHDL & Co. ·

  • Thread

    FSM Beschreibung in VHDL (registered, combinatorial)

    ----------------------- WHEN OTHERS => state <= idle; END CASE; END IF; END PROCESS fsm; [/vhdl] Jetzt finde ich vor allem bei älteren Kollegen immer auch eine kombinatorische Variante, wo alle Signale in einem

    --------------------------- WHEN OTHERS => s_state <= idle; END CASE; END PROCESS fsm; sync : PROCESS(CLK, NRES) BEGIN IF (NRES = '0') THEN state <= idle; ELSIF rising_edge(CLK) THEN state

    FPGA, VHDL & Co. ·Marc M. · ·18 Antworten

  • Thread

    noch keine Angst vor chatGPTs Programmierkünsten

    timer_counter <= RED_ON_TIME; when others => next_state <= GREEN_ON; -- Default state end case; end process; -- LED driving logic green_led <= '1' when (current_state

    timer_counter <= RED_ON_TIME; when others => next_state <= GREEN_ON; -- Default state end case; end process; -- LED driving logic green_led <= '1' when (current_state

    Softwareentwicklung ·Helge S. · ·27 Antworten

  • Thread

    VHDL Anfänger: Problem mit Xilinx9.2

    Du brauchst einen default case beim when (when others), da std-logic ausser 0 und 1 auch unbestimmt, hochohmig usw. annehmen kann.

    Gast wrote: > Du brauchst einen default case beim when (when others), da std-logic > ausser 0 und 1 auch unbestimmt, hochohmig usw. annehmen kann. Danke, bin auch grad fündig geworden. Aber das erklärt nicht, warum das Programm nicht mit bit und bit_vector

    FPGA, VHDL & Co. ·Chris H. · ·6 Antworten

  • Thread

    LCD 2Zeilige Augabe

    end_Addr then address <= address + 1; else address <= (others => '0'); end if; case address is when "00000" => data <= x"68"; when "00001" => data <= x"61"; when "00010" => data <= x"6C"; when "00011" => data <= x"6C"; when "00100" => data <= x"6F"; when others => data <= x"23"; end case; end if; end process; [/vhdl] Schreibt 'Hallo

    FPGA, VHDL & Co. ·Hans Hirsch · ·7 Antworten

  • Datei

    Signed_Multiplier.vhd

    Mult_state; begin process begin wait until rising_edge(clk); if(reset='1') then intOperant_A <= (others => '0'); intOperant_B <= (others => '0'); accu <= (others => '0'); bitCounter <= 0; intbusy <= '0'; Mult_state_reg <= reset_state; else case Mult_state_reg is when reset_state => accu <= (others =>

    in „Ressourcen optimieren für signed multiplier“ · FPGA, VHDL & Co. ·

  • Thread

    Automaten(FSM) und die verschiedenen Prozess Modelle

    Initialisierung (signal state : state_type := s0;) geht natürlich gar nicht. Und dann habe ich auch kein "when others" in der FSM, weil alle definierten States bereits abgehandelt werden. => Ganz böse!!

    <= st3_<name>; end if; when st3_<name> => next_state <= st1_<name>; when others => next_state <= st1_<name>; end case; end process; [/vhdl]

    FPGA, VHDL & Co. ·Andre · ·27 Antworten

  • Thread

    Ecoo-Signal vom PS2 abfangen.

    rxtimeout : integer range 0 to 500000 := 0; signal rxregister : std_logic_vector(10 downto 0) := (others=>'1'); signal datasr : std_logic_vector(1 downto 0) := (others=>'1'); signal clksr : std_logic_vector(1 downto 0) := (others=>'1'); type ps2rxstatetype is (idle, receive, ready);

    clk rxregister <= datasr(1) & rxregister(10 downto 1); end if; case ps2rxstate is when idle => rxregister <= (others=>'1'); rxactive <= '0'; dataready <= '0'; rxtimeout <= 0; if (datasr(1) = '0' and clksr(1) = '1') then ps2rxstate <= receive;

    FPGA, VHDL & Co. ·Peter B. · ·5 Antworten

  • Thread

    VHDL: UART State Machine

    next_state <= s_tx; when AKN => data_out <= x"55"; next_tx_state <= idle; next_state <= s_tx; when s_tx => next_state <= s_tx; if BUSY = '0

    when s_tx_done => if BUSY = '0' then valid_out <= '0'; state <= next_tx_state; end if; when others => state <= idle;

    FPGA, VHDL & Co. ·Hugo P. · ·4 Antworten

  • Thread

    FSM mit taktflankengesteuerten Zustandsübergängen

    else state <= Z1; end if; when others => state <= warten; end case; end if; end process; MFG Falk

    else state <= Z1; end if; when others => state <= warten; end case; end if; end if; Grüße, Kest

    FPGA, VHDL & Co. ·MARK · ·6 Antworten

  • Thread

    Beschreibung funktioniert nach Synthese nicht

    begin if rising_edge(CLK) then case StateMachine is -- Senden when 1 => if NewTransmitACK = '0' then -- Ist der Sender frei? Transmit <= (others => '0'); -- Nachricht pauschal löschen Transmit(7 downto

    begin if rising_edge(CLK) then case StateMachine is -- Senden when 0 => if NewTransmitACK = '0' then -- Ist der Sender frei? Transmit <= (others => '0'); -- Nachricht pauschal löschen Transmit(7 downto

    FPGA, VHDL & Co. ·Steffen Hausinger · ·5 Antworten

  • Datei

    picoboot.vhd

    data input write => '0' -- 0=write 1=read ); com_code_process: process (vsel) begin case vsel is when "111" => com_code <= x"0B"; -- Fast Read when "101" => com_code <= x"03"; -- Read when "110" => com_code <= x"E8"; -- Read Array when others => com_code <= x"E8"; -- Read Array end case; end process

    in „FPGA-bitfile in SPI Seriell Flash programmieren“ · FPGA, VHDL & Co. ·

  • Datei

    lcd.vhd

    (62 downto 56) ; segment_enable <= "1011" ; when others => pixels <= segment_shiftreg(69 downto 63) ; segment_enable <= "0111" ; end case ; end if; end process; process(clk) begin if rising_edge(clk) then if btn_rst = '1' then --Enable Signal für

    in „Fehler bei Case-Anweisung“ · FPGA, VHDL & Co. ·

  • Datei

    Create_Bit_Stream.VHD

    elsif(CLK'event and CLK = '1')then if(GATE = '1' and S_ONE_TIME = '0')then case S_RESET_CONFIG is when "01" => S_RESET <= '1'; when "10" => S_RESET <= '0'; when others => NULL; end case; end if; end if; end process; -- ****** Wandlerwerte in Speicher_A schreiben ****** process (CLR,CLK,RESET_ADC_A,S_REGB

    in „Probleme mit Warnmeldung“ · FPGA, VHDL & Co. ·

  • Datei

    TEM_uni_5_adc_stream.vhd

    ADC_data_ready <= AD7356_56_data_ready; when others => ADC_data <= fifo_counter; ADC_data_ready <= fifo_counter_ready; end case; --------- write to FIFO ------------------------------------ fifo_wr <= '0'; if fsm_fifo = fifo_wait then if ADC_data_ready

    in „Wie Clockdomain crossing für FT232H, wie debuggen?“ · FPGA, VHDL & Co. ·

  • Datei

    user_logic.vhd

    , slv_reg1, slv_reg2, slv_reg3 ) is begin case slv_reg_read_sel is when "1000" => slv_ip2bus_data <= slv_reg0; when "0100" => slv_ip2bus_data <= slv_reg1; when "0010" => slv_ip2bus_data <= slv_reg2; when "0001" => slv_ip2bus_data <= slv_reg3; when others => slv_ip2bus_data

    in „[VHDL] Constant must have a value“ · FPGA, VHDL & Co. ·

  • Thread

    Suche max. Bitvektor

    rising_edge(CLK); comparison <= (value1 > value2) & (value3 > value4); case comparison is when "00" => result <= value2 > value4; when "01" => result <= value2 > value3; when "10" => result <= value1 > value4; when others => result <= value1 > value3; end case; end Behavioral

    process (CLK) comparison <= (value1 > value2) & (value3 > value4); case comparison is when "00" => result <= value2 > value4; when "01" => result <= value2 > value3; when "10" => result <= value1 > value4; when others => result <= value1 > value3; end case; end process;

    FPGA, VHDL & Co. ·pico · ·8 Antworten

  • Datei

    txt_util.vhd

    = 'U'; when 31 => c := 'V'; when 32 => c := 'W'; when 33 => c := 'X'; when 34 => c := 'Y'; when 35 => c := 'Z'; when others => c := '?'; end case; return c; end chr; -- convert integer to string using specified

    in „Rechnen im Hex-Dezimalsystem mit Dezimalanzeige“ · FPGA, VHDL & Co. ·

  • Thread

    FSM Implementierung

    die Zustände S0 bis S3 explizit > auswerten (Variante 1) oder S0 bis S2 explizit und S3 über ein 'others' > abfangen (Variante 2)? Wenn dein Typ genau mit den Zuständen s0..3 definiert ist, und du alle vier möglichen Zustände in der FSM abfrägst, gibt es keine "anderen" Zustände mehr, die mit "when others" abgefragt werden könnten: http://www.lothar-miller.de/s9y/categories/25-when-others *ABER ACHTUNG* Wie diese FSM mit 4 Zuständen /realisiert/ wird, steht auf einem ganz ANDEREN Blatt, nämlich

    FPGA, VHDL & Co. ·O_o · ·10 Antworten

  • Datei

    i2s_shifter_2x_slave.vhdl

    variable bitcnt : integer range 0 to 15; begin if res = '1' then -- reset all buffers in_1_buffer <= (others => '0'); in_2_buffer <= (others => '0'); in_3_buffer <= (others => '0'); in_4_buffer <= (others => '0'); out_1_buffer <= (others => '0'); out_2_buffer <= (others => '0'); out_3_buffer <= (others =>

    in „I2S nach"TheMason" in Betrieb nehmen“ · FPGA, VHDL & Co. ·

  • Thread

    Signal multiplexen

    sel --Internes Auswahlsignal F_out1<= pin_outA1 when sel='0'else pin_outB1 ; --Modul A F_out2<= pin_outA2 when sel='0'else pin_outB2 ; --Modul B --Eingänge-- pin_inA <= F_in when sel='0' else 'Z'; --Modul A pin_inB <= F_in when

    'Z', das geht nur an den Pins direkt, und da nur an > INOUT oder OUT. Wenn, dann auf '0' bzw. (others => '0') bei einem Bus > umschalten. Danke für deine Antwort. Damit ich zwischen beide Eingänge korrekt umschalte wäre dann: --Eingänge-- pin_inA <= F_in when sel='0' else '0';

    FPGA, VHDL & Co. ·Jamal · ·5 Antworten

  • Thread

    [VHDL] Status speichern

    else STATE <= LED_OFF; end if; end process; with STATE select LED(4) <= '0' when LED_ON, '1' when others; achja benutze Xilinx Webpack 11 Bitte um HILFE :-) Danke Grüße balou

    Zähler wait until rising_edge(CLK); if OneSecond='1' then case DIRECTION is when '0' => if (COUNTERX = 63) then -- Überlauf COUNTERX <= 0; else COUNTERX <= COUNTERX + 1; end if; when others => if (COUNTERX = 0) then

    FPGA, VHDL & Co. ·balou · ·18 Antworten

  • Datei

    adc_logic.vhd

    0'; WR_2_EN <= '1' WHEN (RD_CNT = "01" AND RD = '0') ELSE '0'; WR_3_EN <= '1' WHEN (RD_CNT = "10" AND RD = '0') ELSE '0'; D <= X_DATA(7 DOWNTO 0) WHEN WR_1_EN = '1' ELSE (OTHERS => 'Z'); D <= Y_DATA(7 DOWNTO 0) WHEN WR_2_EN = '1' ELSE (OTHERS => 'Z'); D <= X_DATA(11 DOWNTO 8) & Y_DATA(11 DOWNTO 8) WHEN WR_3_EN = '1' ELSE (OTHERS => 'Z'); END Behavioral;

    in „VHDL-Tristatebuffer will nicht“ · FPGA, VHDL & Co. ·

  • Datei

    HyperBus.vhd

    Burst_length: std_logic:='0'; --0: 2Bytes, 1:64Bytes signal Burst_counter_100: unsigned(7 downto 0):=(others => '1'); signal RX_Data_Counter: integer range 0 to 127:=0; signal RX_Data: std_logic_vector(15 downto 0):=(others => '0'); signal TX_Data: std_logic_vector(15 downto 0):=(others => '0'); signal DQ_OUT

    in „HyperBus Ideen“ · FPGA, VHDL & Co. ·

  • Thread

    Tristate Bus Umschaltzeitpunkt

    Das könntest du auch abkürzen und ohne Prozess schreiben: [vhdl] ram_do <= RAM_DB; RAM_DB <= (others => 'Z') when (ram_oe = '0') else ram_di; [/vhdl] Dabei angenommen, do wäre der Eingang ins FPGA und di der Ausgang... :-/ > sollte ich in diese Umschaltung noch jeweils 1 Takt Verzögerung einbauen

    rising_edge(CLK) then ram_oe_last <= ram_oe; end if; end process; RAM_OE <= '1' when (ram_oe_last = '1') else ram_oe; RAM_DB <= (others => 'Z') when (ram_oe = '0') or (ram_oe_last = '0') else ram_di; ram_di <= RAM_DB; [/vhdl] (großgeschrieben sind die Ports nach aussen)

    FPGA, VHDL & Co. ·Andreas · ·9 Antworten