-
Datei
Toplevel.vhd
begin AD7980 : AD7980interface Generic MAP ( SCKLFREQ => 62500000) PORT MAP ( CLK =>TOP_Level_CLK, CNVstart =>CNVsignal, SCLK =>SCLKsignal, MISO =>MISOsignal, DataOut => TOP_Level_DataOut); AD7980Modellinstanz: Modell_AD7980 PORT MAP ( CNV => CNVsignal, SCK => SCLKsignal, MISO => MISOsignal, CLK =>TOP_Level_CLK ); end Behavioral;
-
Datei
Modell_AD7980.vhd
Company: -- Engineer: -- -- Create Date: 09:20:26 08/11/2014 -- Design Name: -- Module Name: Modell_AD7980 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -------------------
-
Datei
AD7980interface.vhd
-- Company: -- Engineer: -- -- Create Date: 17:36:49 08/10/2014 -- Design Name: -- Module Name: AD7980interface - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ----------
-
Datei
ToplevelTB.vhd
49:12 08/11/2014 -- Design Name: -- Module Name: C:/Users/D3XT3ER-Eee/Desktop/Bachelorarbeit/src/AD7980interface/ToplevelTB.vhd -- Project Name: AD7980interface -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: Toplevel -- -- Dependencies: -- -- Revision
-
PDF
ADA4807.pdf
reducing the total supply current for the driver from 1 mA to –65 50 μA. The sampling frequency of the AD7980 can then be –70 reduced to match the power consumption of the AD8603. With )–75 the ADA4807-1/ADA4807-2/ADA4807-4 powered on, the SNR ( and THD are 84.1 dB and −100.3 dB for a 3 V p-p, 1 kHz input
in „LTSpice 24.1.9 AD4807-Simulation schlägt fehl“ · Analoge Elektronik und Schaltungstechnik ·