DCMs am Basys Board

> Ist das Layout misst
Hmmmm...

> oder kann ich die Clock trotzdem an die DCMs leiten?
Ja, mit etwas mehr Skew geht das:

1

The recommended input path to a DCM’s CLKIN input is via one of 

2

the four global buffer inputs (IBUFG) along the same half of the device. 

3

Using the IBUFG path, the delay from the pad, through the global buffer, 

4

to the DCM is eliminated from the deskewed output. Other paths 

5

are possible, however, as shown in Table 3-22.

Also Tabelle 3-22 auf Seite 100 anschauen...

Das geht, aber da kommt dann diese Meldung:

Place:1013 - A clock IOB / DCM component pair have been found that are 
not placed at an optimal clock IOB / DCM site pair.  The clock component 
<Inst_DCM40/DCM_SP_INST> is placed at site <DCM_X1Y3>.  The clock IO/DCM 
site can be paired if they are placed/locked in the same quadrant.  The 
IO component <BusCLK_IN> is placed at site <N9>.  This will not allow 
the use of the fast path between the IO and the Clock buffer. This is 
normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied 
on COMP.PIN <BusCLK_IN.PAD> allowing your design to continue. This 
constraint disables all clock placer rules related to the specified 
COMP.PIN. The use of this override is highly discouraged as it may lead 
to very poor timing results. It is recommended that this error condition 
be corrected in the design.

Aber der 11.1 ist das ein Error, da hört der erst mal auf. Muss man in 
der ucf das CLOCK_DEDICATED_ROUTE auf false setzen für das Signal.