Hallo,
ich habe hier mal wieder ein herbes Problem mit TWI. Kommunizieren
sollen zwei ATMega8 untereinander (später auch mehr). Für den Master
verwende ich die Lib von Peter Fleury.
Den Slave habe ich Interruptbasiert selbst geschrieben.
Master:
1 | while(1)
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2 | {
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3 | uint8_t ret;
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4 | ret = i2c_start(0x10+I2C_READ); // set device address and write mode
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5 | if(ret)
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6 | {
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7 | i2c_stop();
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8 | uart_putcc("Failed to read!\r\n");
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9 | }
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10 | else
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11 | {
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12 | if(i2c_readAck()!=2) uart_putc('E');
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13 | if(i2c_readAck()!=2) uart_putc('E');
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14 | if(i2c_readAck()!=2) uart_putc('E');
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15 | if(i2c_readAck()!=2) uart_putc('E');
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16 | if(i2c_readAck()!=2) uart_putc('E');
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17 | if(i2c_readNak()!=2) uart_putc('E');
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18 | i2c_stop();
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19 | uart_putc('r');
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20 | }
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21 | sleep_10ms(100);
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22 | }
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Slave:
1 | #include "TWISlave.h"
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2 |
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3 | uint8_t counter;
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4 | uint8_t sender;
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5 | uint8_t volatile watchdog;
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6 |
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7 | void twi_init()
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8 | {
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9 | TWAR= 0x10; //Adresse setzen
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10 | TWCR &= ~(1<<TWSTA)|(1<<TWSTO);
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11 | TWCR|= (1<<TWEA) | (1<<TWEN)|(1<<TWIE);
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12 |
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13 | //fifo_init(&twi_fifo_out, twi_buffer_out, TWI_BUFFERSIZE_OUT);
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14 | //fifo_init(&twi_fifo_in, twi_buffer_in, TWI_BUFFERSIZE_IN);
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15 | watchdog=0;
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16 | counter=0;
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17 | sender=0;
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18 | }
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19 |
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20 | ISR(TWI_vect)
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21 | {
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22 | uint8_t data, event;
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23 | event=TWSR & 0xF8;
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24 | switch (event)
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25 | {
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26 | case 0x00: // Error detected
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27 | counter++;
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28 | uart_putcc("TWI: Error!\r\n");
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29 | break;
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30 |
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31 | /* Transmitter */
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32 | case TW_ST_DATA_NACK: // last byte send, NACK received
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33 | TWDR=0x01;
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34 | TWCR_ACK;
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35 | uart_putc('w');
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36 | break;
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37 | case TW_ST_SLA_ACK: // slave was adressed, Master wants to read first byte
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38 | counter=0;
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39 | uart_putc('a');
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40 | case TW_ST_DATA_ACK: // master wants to read next byte...
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41 | TWDR=0x02;
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42 | counter++;
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43 | TWCR_ACK
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44 | uart_putc('s');
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45 | break;
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46 | case TW_ST_LAST_DATA: //0xC8 last data byte in TWDR has been transmitted (TWEA = 0); ACK has been received
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47 | //TWDR=0x03;
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48 | TWCR_ACK;
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49 | uart_putc('l');
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50 | break;
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51 |
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52 | /* Reciver */
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53 | case TW_SR_SLA_ACK: // 0x60 slave was adressed as receiver, no byte send yet
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54 | TWCR_ACK;
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55 | break;
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56 | case TW_SR_DATA_ACK: // got data from master
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57 | data=TWDR;
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58 | TWCR_ACK
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59 | //fifo_put(&twi_fifo_in, data);
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60 | break;
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61 | case TW_SR_DATA_NACK: //0x88
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62 | case TW_SR_STOP:
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63 | TWCR_ACK
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64 | break;
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65 | default:
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66 | counter++;
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67 | uart_putcc("TWI: unknown event: ");
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68 | uart_puti(event);
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69 | uart_putcc("\r\n");
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70 | break;
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71 | }
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72 | }
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Nach ein paar Übertragungen (i.d.R. 4) friert alles ein und nichts
passiert mehr. SDA und SCL liegen auf Low, wenn ich den Master rausziehe
sind sie immernoch auf Low, wenn ich dann noch den Slave rausziehe nicht
mehr, also muss der Slave Mist bauen würde ich sagen.
Kann jemand da was erkennen? Bin am verzweifeln :(
Edit:
Ausgabe Slave: asssssswasssssswasssssswassssssw
Ausgabe Master: rrrr
