1 | main.elf: file format elf32-avr
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2 |
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3 | Sections:
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4 | Idx Name Size VMA LMA File off Algn
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5 | 0 .text 000000a0 00000000 00000000 00000074 2**1
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6 | CONTENTS, ALLOC, LOAD, READONLY, CODE
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7 | 1 .bss 00000001 00800060 00800060 00000114 2**0
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8 | ALLOC
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9 | 2 .stab 00000378 00000000 00000000 00000114 2**2
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10 | CONTENTS, READONLY, DEBUGGING
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11 | 3 .stabstr 00000054 00000000 00000000 0000048c 2**0
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12 | CONTENTS, READONLY, DEBUGGING
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13 | 4 .debug_aranges 00000014 00000000 00000000 000004e0 2**0
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14 | CONTENTS, READONLY, DEBUGGING
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15 | 5 .debug_pubnames 0000001b 00000000 00000000 000004f4 2**0
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16 | CONTENTS, READONLY, DEBUGGING
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17 | 6 .debug_info 0000009c 00000000 00000000 0000050f 2**0
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18 | CONTENTS, READONLY, DEBUGGING
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19 | 7 .debug_abbrev 00000077 00000000 00000000 000005ab 2**0
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20 | CONTENTS, READONLY, DEBUGGING
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21 | 8 .debug_line 000000e6 00000000 00000000 00000622 2**0
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22 | CONTENTS, READONLY, DEBUGGING
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23 | 9 .debug_frame 00000028 00000000 00000000 00000708 2**0
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24 | CONTENTS, READONLY, DEBUGGING
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25 | 10 .debug_str 000000b1 00000000 00000000 00000730 2**0
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26 | CONTENTS, READONLY, DEBUGGING
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27 |
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28 | Disassembly of section .text:
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29 |
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30 | 00000000 <__vectors>:
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31 | 0: 12 c0 rjmp .+36 ; 0x26 <__ctors_end>
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32 | 2: 2c c0 rjmp .+88 ; 0x5c <__bad_interrupt>
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33 | 4: 2b c0 rjmp .+86 ; 0x5c <__bad_interrupt>
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34 | 6: 2a c0 rjmp .+84 ; 0x5c <__bad_interrupt>
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35 | 8: 29 c0 rjmp .+82 ; 0x5c <__bad_interrupt>
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36 | a: 28 c0 rjmp .+80 ; 0x5c <__bad_interrupt>
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37 | c: 27 c0 rjmp .+78 ; 0x5c <__bad_interrupt>
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38 | e: 26 c0 rjmp .+76 ; 0x5c <__bad_interrupt>
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39 | 10: 25 c0 rjmp .+74 ; 0x5c <__bad_interrupt>
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40 | 12: 24 c0 rjmp .+72 ; 0x5c <__bad_interrupt>
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41 | 14: 23 c0 rjmp .+70 ; 0x5c <__bad_interrupt>
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42 | 16: 22 c0 rjmp .+68 ; 0x5c <__bad_interrupt>
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43 | 18: 21 c0 rjmp .+66 ; 0x5c <__bad_interrupt>
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44 | 1a: 20 c0 rjmp .+64 ; 0x5c <__bad_interrupt>
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45 | 1c: 1f c0 rjmp .+62 ; 0x5c <__bad_interrupt>
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46 | 1e: 1e c0 rjmp .+60 ; 0x5c <__bad_interrupt>
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47 | 20: 1d c0 rjmp .+58 ; 0x5c <__bad_interrupt>
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48 | 22: 1c c0 rjmp .+56 ; 0x5c <__bad_interrupt>
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49 | 24: 1b c0 rjmp .+54 ; 0x5c <__bad_interrupt>
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50 |
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51 | 00000026 <__ctors_end>:
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52 | 26: 11 24 eor r1, r1
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53 | 28: 1f be out 0x3f, r1 ; 63
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54 | 2a: cf e5 ldi r28, 0x5F ; 95
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55 | 2c: d4 e0 ldi r29, 0x04 ; 4
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56 | 2e: de bf out 0x3e, r29 ; 62
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57 | 30: cd bf out 0x3d, r28 ; 61
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58 |
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59 | 00000032 <__do_copy_data>:
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60 | 32: 10 e0 ldi r17, 0x00 ; 0
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61 | 34: a0 e6 ldi r26, 0x60 ; 96
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62 | 36: b0 e0 ldi r27, 0x00 ; 0
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63 | 38: e0 ea ldi r30, 0xA0 ; 160
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64 | 3a: f0 e0 ldi r31, 0x00 ; 0
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65 | 3c: 02 c0 rjmp .+4 ; 0x42 <.do_copy_data_start>
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66 |
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67 | 0000003e <.do_copy_data_loop>:
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68 | 3e: 05 90 lpm r0, Z+
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69 | 40: 0d 92 st X+, r0
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70 |
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71 | 00000042 <.do_copy_data_start>:
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72 | 42: a0 36 cpi r26, 0x60 ; 96
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73 | 44: b1 07 cpc r27, r17
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74 | 46: d9 f7 brne .-10 ; 0x3e <.do_copy_data_loop>
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75 |
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76 | 00000048 <__do_clear_bss>:
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77 | 48: 10 e0 ldi r17, 0x00 ; 0
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78 | 4a: a0 e6 ldi r26, 0x60 ; 96
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79 | 4c: b0 e0 ldi r27, 0x00 ; 0
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80 | 4e: 01 c0 rjmp .+2 ; 0x52 <.do_clear_bss_start>
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81 |
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82 | 00000050 <.do_clear_bss_loop>:
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83 | 50: 1d 92 st X+, r1
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84 |
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85 | 00000052 <.do_clear_bss_start>:
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86 | 52: a1 36 cpi r26, 0x61 ; 97
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87 | 54: b1 07 cpc r27, r17
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88 | 56: e1 f7 brne .-8 ; 0x50 <.do_clear_bss_loop>
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89 | 58: 11 d0 rcall .+34 ; 0x7c <main>
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90 | 5a: 21 c0 rjmp .+66 ; 0x9e <_exit>
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91 |
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92 | 0000005c <__bad_interrupt>:
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93 | 5c: d1 cf rjmp .-94 ; 0x0 <__vectors>
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94 |
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95 | 0000005e <__vector_4>:
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96 | volatile uint8_t flag;
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97 |
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98 |
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99 | // Timer2 overflow Interrupt
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100 | // hier wird der Hauptschleife ein neuer Timerinterrupt signalisiert
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101 | ISR( TIMER2_OVF_vect ) {
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102 | 5e: 1f 92 push r1
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103 | 60: 0f 92 push r0
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104 | 62: 0f b6 in r0, 0x3f ; 63
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105 | 64: 0f 92 push r0
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106 | 66: 11 24 eor r1, r1
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107 | 68: 8f 93 push r24
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108 | flag = 1;
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109 | 6a: 81 e0 ldi r24, 0x01 ; 1
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110 | 6c: 80 93 60 00 sts 0x0060, r24
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111 | 70: 8f 91 pop r24
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112 | 72: 0f 90 pop r0
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113 | 74: 0f be out 0x3f, r0 ; 63
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114 | 76: 0f 90 pop r0
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115 | 78: 1f 90 pop r1
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116 | 7a: 18 95 reti
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117 |
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118 | 0000007c <main>:
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119 | }
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120 |
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121 | int main(void) {
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122 |
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123 | // IO konfigurieren
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124 | DDRD = 0xFF;
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125 | 7c: 8f ef ldi r24, 0xFF ; 255
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126 | 7e: 81 bb out 0x11, r24 ; 17
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127 |
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128 | // Timer2 konfigurieren
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129 | TCCR2 = (1 << CS22) | (1 << CS21);
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130 | 80: 86 e0 ldi r24, 0x06 ; 6
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131 | 82: 85 bd out 0x25, r24 ; 37
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132 | TIMSK = (1 << TOIE2);
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133 | 84: 80 e4 ldi r24, 0x40 ; 64
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134 | 86: 89 bf out 0x39, r24 ; 57
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135 |
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136 | // Interrupts freigeben
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137 | sei();
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138 | 88: 78 94 sei
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139 |
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140 | // Endlose Hauptschleife
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141 | while(1) {
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142 | if (flag == 1) { // Neuer Timerzyklus ?
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143 | 8a: 90 91 60 00 lds r25, 0x0060
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144 | 8e: 91 30 cpi r25, 0x01 ; 1
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145 | 90: e1 f7 brne .-8 ; 0x8a <main+0xe>
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146 | flag = 0;
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147 | 92: 10 92 60 00 sts 0x0060, r1
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148 |
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149 | PORTD ^= (1 << PD0); // LED toggeln
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150 | 96: 82 b3 in r24, 0x12 ; 18
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151 | 98: 89 27 eor r24, r25
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152 | 9a: 82 bb out 0x12, r24 ; 18
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153 | 9c: f6 cf rjmp .-20 ; 0x8a <main+0xe>
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154 |
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155 | 0000009e <_exit>:
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156 | 9e: ff cf rjmp .-2 ; 0x9e <_exit>
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