So,
ich habe bis Ende des Sommers eine Prüfungsaufgabe mittels VHDL und
Quartus II zu lösen - es soll eine digitale Weckuhr rauskommen.
Jetzt hänge ich hier da und irgendwie funktioniert garnichts.
Ich hänge mal meinen VHDL-Code ran, in der Hoffnung mir kann jemand
helfen (sorry - ist schon ziemlich verbastelt).
Wie man erkennen kann, soll es ein 4bit-Synchron-Zähler sein, der von
0-15,0 zählt.
Problem: Der Zähler zählt garnichts - irgendwie geht mit dem Ding
nichts.
Nehme ich den "CLK"-Teil (NICHT den clk1s-Teil) raus, dann bekomme ich
zwar was an den Ausgängen (a-d) zu sehen - aber das hat rein garnichts
mit einem Zähler zu tun, da kommt irgendwas lustig verwurschteltes raus.
Bei Bedarf kann auch gerne das gesamte Projekt nachgereicht werden.
Hilfe ?!
1 | -- Generated by Quartus II Version 9.0 (Build Build 132 02/25/2009)
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2 | -- Created on Sun May 09 21:17:32 2010
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3 |
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4 | LIBRARY ieee;
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5 | USE ieee.std_logic_1164.all;
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6 |
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7 |
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8 | -- Entity Declaration
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9 |
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10 | ENTITY dec_sekunden IS
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11 | -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
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12 | PORT
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13 | (
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14 | clk1s : in std_logic;
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15 | reset : in std_logic;
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16 | a : out std_logic;
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17 | b : out std_logic;
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18 | c : out std_logic;
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19 | d : out std_logic
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20 | );
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21 | -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
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22 |
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23 | END dec_sekunden;
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24 |
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25 |
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26 | -- Architecture Body
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27 |
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28 | architecture dec_sekunden_architecture of dec_sekunden is
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29 | -- Build an enumerated type for the state machine
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30 | type state_type is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15);
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31 | -- Register to hold the current state
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32 | signal state: state_type;
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33 | signal clk: integer range 0 to 100;
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34 |
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35 | begin
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36 | -- Logic to advance to the next state
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37 | process (clk1s, reset, state, clk) begin
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38 | if reset = '1' then
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39 | state <= s0;
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40 | clk <= 0;
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41 | end if;
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42 | if clk < 100 then
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43 | clk <= clk+1;
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44 | end if;
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45 | if clk > 99 and clk1s = '1' then
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46 | case state is
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47 | when s0 =>
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48 | state <= s1;
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49 | when s1 =>
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50 | state <= s2;
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51 | when s2 =>
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52 | state <= s3;
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53 | when s3 =>
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54 | state <= s4;
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55 | when s4 =>
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56 | state <= s5;
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57 | when s5 =>
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58 | state <= s6;
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59 | when s6=>
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60 | state <= s7;
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61 | when s7=>
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62 | state <= s8;
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63 | when s8=>
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64 | state <= s9;
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65 | when s9 =>
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66 | state <= s10;
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67 | when s10 =>
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68 | state <= s11;
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69 | when s11 =>
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70 | state <= s12;
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71 | when s12=>
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72 | state <= s13;
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73 | when s13=>
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74 | state <= s14;
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75 | when s14=>
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76 | state <= s15;
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77 | when s15 =>
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78 | state <= s0;
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79 | end case;
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80 | end if;
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81 | end process;
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82 |
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83 | -- Output depends solely on the current state
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84 | process (state) begin
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85 | case state is
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86 | when s0 => -- dec 0
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87 | a <= '0';
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88 | b <= '0';
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89 | c <= '0';
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90 | -- d <= '0';
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91 | when s1 => -- dec 1
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92 | a <= '0';
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93 | b <= '0';
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94 | c <= '0';
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95 | d <= '1';
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96 | when s2 => -- dec 2
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97 | a <= '0';
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98 | b <= '0';
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99 | c <= '1';
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100 | d <= '0';
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101 | when s3 => -- dec 3
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102 | a <= '0';
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103 | b <= '0';
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104 | c <= '1';
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105 | d <= '1';
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106 | when s4 => -- dec 4
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107 | a <= '0';
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108 | b <= '1';
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109 | c <= '0';
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110 | d <= '0';
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111 | when s5 => -- dec 5
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112 | a <= '0';
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113 | b <= '1';
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114 | c <= '0';
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115 | d <= '1';
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116 | when s6 => -- dec 6
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117 | a <= '0';
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118 | b <= '1';
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119 | c <= '1';
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120 | d <= '0';
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121 | when s7 => -- dec 7
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122 | a <= '0';
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123 | b <= '1';
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124 | c <= '1';
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125 | d <= '1';
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126 | when s8 => -- dec 8
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127 | a <= '1';
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128 | b <= '0';
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129 | c <= '0';
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130 | d <= '0';
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131 | when s9 => -- dec 9
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132 | a <= '1';
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133 | b <= '0';
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134 | c <= '0';
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135 | d <= '1';
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136 | when s10 => -- dec 10
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137 | a <= '1';
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138 | b <= '0';
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139 | c <= '1';
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140 | d <= '0';
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141 | when s11 => -- dec 11
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142 | a <= '1';
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143 | b <= '0';
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144 | c <= '1';
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145 | d <= '1';
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146 | when s12 => -- dec 12
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147 | a <= '1';
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148 | b <= '1';
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149 | c <= '0';
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150 | d <= '0';
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151 | when s13 => -- dec 13
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152 | a <= '1';
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153 | b <= '1';
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154 | c <= '0';
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155 | d <= '1';
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156 | when s14 => -- dec 14
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157 | a <= '1';
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158 | b <= '1';
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159 | c <= '1';
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160 | d <= '0';
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161 | when s15 => -- dec 15
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162 | a <= '1';
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163 | b <= '1';
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164 | c <= '1';
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165 | d <= '1';
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166 | end case;
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167 | end process;
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168 |
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169 | end dec_sekunden_architecture;
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