Gast
#1725839
Hallo,
ich bin VHLD-Anfänger und bin gerade dabei, eine Aufgabe zu lösen, in
dem ein Zähler einen 7 Segment Anzeige füttert.
Der Zähler macht genau was er soll, dieser hat einen clk,rst, und
enable.
Mein Problem liegt darin, das Ausgangssignal des Zählers, in die
7Segment anzeige zu führen.
Der Zähler und der Code für die 7 Segment Anzeige, werden richtig
kompiliert.
Der bei der Testbench kommen folgende Fehler:
tb_7segment.vhd(32): (vcom-1027) Number of positional association
elements (2) exceeds number of formals (1).
tb_7segment.vhd(32): (vcom-1272) Length of formal "display" is 7; length
of actual is 4.
Danke im voraus
Der Code sieht so aus:
Zähler:
------------------------------------------------------------------------
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity zaehler is
port(clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
q: out std_logic_vector(3 downto 0) );
end zaehler;
architecture bevofzaehler of zaehler is
begin
p1: process(clk, rst, enable)
variable var : std_logic_vector(3 downto 0);
begin
if(rst = '1') then
q <= "0000";
var := "0000";
else
if(clk'event and clk='1') then
if(enable = '0') then
q <= var;
else
if (var = "1001") then
var := "0000";
else
var := var + '1';
end if;
q <= var;
end if;
end if;
end if;
end process;
end bevofzaehler;
------------------------------------------------------------------------
--
------------------------------------------------------------------------
--
7Segment-Anzeige
------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity segment is
port(q : in std_logic_vector(3 downto 0);
display: out std_logic_vector(6 downto 0) );
end segment;
architecture bevofsegment of segment is
signal clk, rst, enable : std_logic ;
signal s : std_logic_vector(3 downto 0);
component zaehler
port(clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
q: out std_logic_vector(3 downto 0) );
end component;
begin
z1:zaehler port map(clk, rst, enable, s);
p2:process(s)
begin
case s is
when "0000" =>
display <= "1111110";
when "0001" =>
display <= "0110000";
when "0010" =>
display <= "1101101";
when "0011" =>
display <= "1111001";
when "0100" =>
display <= "0110011";
when "0101" =>
display <= "1011011";
when "0110" =>
display <= "1011111";
when "0111" =>
display <= "1110000";
when "1000" =>
display <= "1111111";
when "1001" =>
display <= "1111011";
when others =>
display <= "0000001";
end case;
end process p2;
end bevofsegment;
------------------------------------------------------------------------
--
------------------------------------------------------------------------
--
Testbench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_segment is
end test_segment;
architecture benchsegment of test_segment is
signal clk, rst, enable : std_logic;
signal s : std_logic_vector(3 downto 0);
signal display : std_logic_vector(6 downto 0);
component segment
port(
display: out std_logic_vector(6 downto 0) );
end component;
component zaehler
port(clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
q: out std_logic_vector(3 downto 0) );
end component;
begin
DUT0:zaehler port map(clk, rst, enable, s);
DUT1:segment port map(s, display);
rst <= '0', '1' after 20 ns;
enable <= '0', '1' after 40 ns;
process
begin
wait for 20 ns;
clk <= not clk;
end process;
end benchsegment;
------------------------------------------------------------------------
--
