AT91SAM7S64 MainClock lässt sich nicht verändern

void LowLevelInit(void)

{

   int            i;

   AT91PS_PMC     pPMC = AT91C_BASE_PMC;

    //* Set Flash Wait sate

  //  Single Cycle Access at Up to 30 MHz, or 40

  //  if MCK = 48054841 I have 50 Cycle for 1 usecond ( flied MC_FMR->FMCN

  AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(50 <<16)) | AT91C_MC_FWS_1FWS;

    //* Watchdog Disable

  AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;

  //* Set MCK at 48 054 841

    // 1 Enabling the Main Oscillator:

  // SCK = 1/32768 = 30.51 uSecond

  // Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms

  pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x09 <<8) | AT91C_CKGR_MOSCEN ));

  // Wait the startup time

  while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));

  // PMC Clock Generator PLL Register setup

  //

  // The following settings are used:  DIV = 14

  //                                   MUL = 72

  //                                   PLLCOUNT = 10

  //

  // Main Clock (MAINCK from crystal oscillator) = 18432000 hz (see AT91SAM7-EK schematic)

  // MAINCK / DIV = 18432000/14 = 1316571 hz

  // PLLCK = 1316571 * (MUL + 1) = 1316571 * (72 + 1) = 1316571 * 73 = 96109683 hz

  //

  // PLLCOUNT = number of slow clock cycles before the LOCK bit is set

  //            in PMC_SR after CKGR_PLLR is written.

  //

  // PLLCOUNT = 10

  //

  // OUT = 0 (not used)

        // 16 MHz * (5+1) / 1 = 96 MHz

  pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 1) |    // 14

                      (AT91C_CKGR_PLLCOUNT & (10<<8)) |    // 10

                      (AT91C_CKGR_MUL & (5<<16)));    // 72

  // Wait the startup time (until PMC Status register LOCK bit is set)

   while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));

  // PMC Master Clock (MCK) Register setup

  //

  // CSS  = 3  (PLLCK clock selected)

  //

  // PRES = 1  (MCK = PLLCK / 2) = 96109683/2 = 48054841 hz

  //

  // Note: Master Clock  MCK = 48054841 hz  (this is the CPU clock speed)

  pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2;

  // Set up the default interrupts handler vectors

  AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler;

  for (i=1;i < 31; i++)

  {

      AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler;

  }

  AT91C_BASE_AIC->AIC_SPU  = (int) AT91F_Spurious_handler;

}