Anfängerfrage zu FSMs

entity test is

  port(

  clk : in std_logic;

  rst : in std_logic;

  led1 : out std_logic);

end entity test;

architecture Behavioral of test is  

  signal cnt: integer range 0 to 7;

  type fsmStates is (s1, s2);

  signal state : fsmStates;

begin

process(clk)

begin

  if clk'event and clk = '1' then

    if rst = '1' then

      state <= s1;

      cnt <= 0;

      led1 <= '0';

    else

    case state is

     when s1 =>

       state <= s1;

       led1 <= '1';

       if cnt < 7 then

         cnt <= cnt+1;

       else

         cnt <= 0;

         state <= s2;

       end if;

     when s2 =>

       state <= s2;

       led1 <= '0';

       if cnt < 7 then

        cnt <= cnt+1;

       else

         cnt <= 1;

         state <= s1;

       end if;

      end case;    

    end if;

  end if;

end process;

end Behavioral;