Hallo zusammen,
ich bin VHDL neuling und wollte mir in Quartus 2 einmal aus einem VHDL
beispiel die logikbausteinverknüpfung synthetisieren und anzeigen
lassen. der code wird erfolgreich kompiliert, ich weiß nun aber nicht,
wie ich die synthese anzeigen lassen kann (um zu verdeutlichen was ich
mit synthese meine: "schaltplan" aus ands, ors, flipflops, etc).
Kann mir dabei jemand helfen? Ich würde gerne wissen, was quartus 2 aus
dem VHDL code macht:
1 | -- Mealy Machine
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2 | ENTITY test IS
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3 | PORT (x, clock : IN bit;
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4 | z : OUT bit);
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5 | END test;
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6 | ARCHITECTURE behavioral OF test IS
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7 | TYPE state_type IS (s0, s1, s2, s3);
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8 | SIGNAL current_state, next_state:
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9 | state_type;
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10 | BEGIN
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11 | -- process to hold synchronous elements
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12 | sync: PROCESS
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13 | BEGIN
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14 | WAIT UNTIL clock'EVENT AND clock='1';
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15 | current_state <= next_state;
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16 | END PROCESS;
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17 | -- process to hold combinational logic
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18 | comb: PROCESS (current_state, x)
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19 | BEGIN
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20 | CASE current_state IS
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21 | WHEN s0 =>
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22 | IF x='0' THEN
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23 | z <= '0';
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24 | next_state <= s0;
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25 | ELSE
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26 | z <= '1';
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27 | next_state <= s2;
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28 | END IF;
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29 | WHEN s1 =>
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30 | IF x='0' THEN
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31 | z <= '0';
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32 | next_state <= s0;
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33 | ELSE
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34 | z <= '0';
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35 | next_state <= s2;
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36 | END IF;
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37 | WHEN s2 =>
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38 | IF x='0' THEN
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39 | z <= '1';
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40 | next_state <= s2;
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41 | ELSE
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42 | z <= '0';
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43 | next_state <= s3;
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44 | END IF;
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45 | WHEN s3 =>
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46 | IF x='0' THEN
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47 | z <= '0';
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48 | next_state <= s3;
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49 | ELSE
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50 | z <= '1';
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51 | next_state <= s1;
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52 | END IF;
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53 | END CASE;
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54 | END PROCESS;
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55 | END behavioral;
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