Hi everyone, I have sucessfully integrated the Altera Avalon MM Read Master template. However, this only works properly up to the length of 20. (word size is 32 bit) When I define the transfer length to be 24, i.e. 6 words, then there are only 5 dataavailable assertions with 5 buffered data. What I find interesting is, that the signal early_done does get asserted, meaning the last read is actually posted, but the signal done is never asserted, so somehow the result cannot be returned. I already used a FIFO of size 64, so should be big enough I think. Is this a known issue? Or anyone an idea what the problem could be? Best regards, Jimmy
Did you try to simulate your design? Or did you just test it on hardware? Duke
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