1 | void DMA0_512bytes_transfer_to_SSP0(u32 buf_offset,uint32 count){
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2 | LPC_SSP0->DMACR=3;// ->DMACR=2;//tx en//176x
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3 | LPC_SC->DMAREQSEL = 0;// SC_DMASEL_timer0_MATCH1_notUART0rx;//i.V.m. DMAC_SRC_PERIP(9)LPC_GPDMACH0->DMACCConfig
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4 | LPC_SC->PCONP |= (1<<29);//Enable clock to DMA controller
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5 | LPC_GPDMA->DMACConfig=DMAC_CTRL_ENABLE;
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6 |
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7 | LPC_GPDMACH0->DMACCSrcAddr = buffer+(buf_offset);
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8 | LPC_GPDMACH0->DMACCDestAddr = &(LPC_SSP0->DR);
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9 | LPC_GPDMACH0->DMACCControl =(0
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10 | |DMAC_CHAN_INT_TC_EN
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11 | |DMAC_CHAN_SRC_AUTOINC
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12 | |DMAC_CHAN_SRC_WIDTH_8
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13 | |DMAC_CHAN_SRC_BURST_1
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14 | // |DMAC_CHAN_DEST_AUTOINC
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15 | |DMAC_CHAN_DEST_WIDTH_8
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16 | |DMAC_CHAN_DEST_BURST_1
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17 | |DMAC_CHAN_TRANSFER_SIZE(count)
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18 | );
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19 |
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20 | LPC_GPDMACH0->DMACCConfig =(0
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21 | | DMA_CHAN_IE_ITC_EN
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22 | // | DMAC_CHAN_FLOW_D_M2M
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23 | | DMAC_CHAN_FLOW_D_M2P
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24 | // | DMAC_CHAN_FLOW_D_P2M
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25 | // | DMAC_SRC_PERIP(DMA_REQUEST_SSP0_TX)
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26 | // | DMAC_SRC_PERIP(9)
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27 | // | DMAC_SRC_PERIP(DMA_REQUEST_SSP0_RX)
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28 | | DMAC_DEST_PERIP(DMA_REQUEST_SSP0_TX)
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29 | // | DMAC_DEST_PERIP(DMA_REQUEST_SSP0_RX)
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30 | );
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31 | }
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32 |
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33 |
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34 |
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35 | v u32 DMATCCount=0,DMAErrCount,DMA_STATUS;
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36 | void DMA_IRQHandler(void)
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37 | {
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38 | uint32_t regVal;
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39 |
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40 | regVal = LPC_GPDMA->DMACIntStat;
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41 | if ( regVal )//not error
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42 | {
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43 | DMATCCount++;
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44 | LPC_GPDMA->DMACIntTCClear = regVal;
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45 |
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46 | if ( regVal & (0x01<<0) )//channel0 ready 512Datenbytes
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47 | {
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48 | DMA_STATUS = 1;
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49 | DMA3_transfer_from_SSP0(16);//rxfifo leeren
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50 | }
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51 | else if ( regVal & (0x01<<3) )//rxfifo leeren
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52 | {
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53 | DMA_STATUS = 2;
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54 | DMA2_3bytes_transfer_to_SSP0();//++++++ crc, response
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55 |
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56 | }
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57 | else if ( regVal & (0x01<<2) )//++++++ crc, response
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58 | {
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59 | DMA_STATUS = 3;
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60 | }
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61 | else if ( regVal & (0x01<<3) )
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62 | {
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63 | DMA_STATUS = 4;
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64 | }
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65 | }
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66 |
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67 | regVal = LPC_GPDMA->DMACIntErrStat;
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68 | if ( regVal )
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69 | {
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70 | DMAErrCount++;
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71 | LPC_GPDMA->DMACIntErrClr = regVal;
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72 | }
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73 | return;
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74 | }
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75 |
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76 |
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77 |
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78 | static
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79 | int xmit_datablock_kk ( /* 1:OK, 0:Failed */
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80 | const BYTE *buff, /* Ponter to 512 byte data to be sent */
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81 | BYTE token /* Token */){
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82 | u32 zl;
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83 | UINT n = 512,btx=512;
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84 | WORD d;
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85 | BYTE resp,tmp;
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86 | // if (!wait_ready(500)) return 0; /* Wait for card ready */
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87 | DMA_STATUS=0;
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88 | while(tmp!=0xff){tmp=xchg_spi(0xff);zl++;}
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89 | xchg_spi(token); /* Send token */
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90 |
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91 |
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92 | //DMA1_1bytes_transfer_to_SSP0();
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93 | //while(!(LPC_GPDMA->DMACIntTCStat && (1<<1)));
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94 |
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95 |
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96 | //++++++ Datentransfer
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97 | //SSPxCR0 = 0x000F; /* Select 16-bit mode */
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98 | SSPxCR0 = 0x0007; /* Select 8-bit mode */
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99 | DMA0_512bytes_transfer_to_SSP0(0,512); //buffer_offset,Anzahl_bytes
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100 | while(!(LPC_GPDMA->DMACIntTCStat && (1<<0)));
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101 | /* for (n = 0; n < 512; n++) { // Push 8 frames into pipeline
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102 | d = *buff++;
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103 | SSPxDR = d;
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104 | while ((SSPxSR & SSPSR_isBSY)) ;//0,55
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105 | }*/
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106 |
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107 | //++++++ rx_fifo leeren, 8 frames, bei DMA 16 frames
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108 | DMA3_transfer_from_SSP0(16);
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109 | while(!(LPC_GPDMA->DMACIntTCStat && (1<<3)));
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110 | /*for (n = 0; n < 8; n++) {
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111 | // while (!(SSPxSR & SSPSR_RNE)) ;
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112 | while ((SSPxSR & SSPSR_isBSY)) ;//0,55
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113 | tmp=SSPxDR;
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114 | }
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115 | */
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116 |
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117 | //++++++ crc, response
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118 | DMA2_3bytes_transfer_to_SSP0();
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119 | while(!(LPC_GPDMA->DMACIntTCStat && (1<<2)));
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120 | /* xchg_spi(0xFF);
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121 | xchg_spi(0xFF); // Dummy CRC
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122 | xchg_spi(0xFF); // Receive data resp
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123 | */
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124 | // return 1;
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125 | lgi(6,1,zl);
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126 | }
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