Hallo, ich habe eine RAM-Compenente gebastelt.
Die Datenübergabe findet sofort statt, nachdem ich es in den DE1 geladen
habe, ohne den Schiebeschalter SW(0) zu betätigen.
Woran liegt das bitte ?
Danke.
Gruss
Diese VHDL bindet die Sync_ram.vhdl ein:
1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.numeric_std.all;
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4 |
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5 | entity c_sync_ram is port(
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6 | clock : in std_logic;
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7 | led_g : out STD_LOGIC_VECTOR(7 downto 0);
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8 | sw : in STD_LOGIC_VECTOR(0 downto 0)
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9 | );
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10 | end c_sync_ram;
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11 |
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12 | architecture Behavioral of c_sync_ram is
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13 |
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14 | signal we : STD_LOGIC;
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15 | signal address : std_logic_vector (7 downto 0);
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16 | signal datain : std_logic_vector (7 downto 0);
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17 | signal dataout : std_logic_vector (7 downto 0);
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18 | signal read_address : std_logic_vector(7 downto 0);
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19 |
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20 | component sync_ram port(
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21 | we : in STD_LOGIC;
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22 | address : in std_logic_vector (7 downto 0);
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23 | datain : in std_logic_vector (7 downto 0);
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24 | dataout : inout std_logic_vector (7 downto 0);
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25 | clock : in std_logic;
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26 | read_address : in std_logic_vector(7 downto 0)
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27 | );
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28 | end component;
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29 |
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30 | begin
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31 | io1 : sync_ram port map(we,address,datain,dataout,clock,read_address);
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32 |
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33 | process(clock)
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34 | begin
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35 | if rising_edge(clock) then
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36 | if sw(0)='1' then
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37 | we <='1';
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38 | address<="00001111";
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39 | datain<="11000011";
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40 | else
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41 | we<='0';
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42 | read_address<="00001111";
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43 | end if;
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44 | end if;
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45 | end process;
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46 |
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47 | led_g<=dataout;
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48 |
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49 | end Behavioral;
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sync_ram:
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.all;
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3 | use IEEE.Numeric_Std.all;
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4 |
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5 | entity sync_ram is
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6 | port (
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7 | clock : in std_logic;
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8 | we : in std_logic;
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9 | address : in std_logic_vector (7 downto 0);
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10 | datain : in std_logic_vector (7 downto 0);
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11 | dataout : out std_logic_vector (7 downto 0);
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12 | read_address : in std_logic_vector(7 downto 0)
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13 | );
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14 | end entity sync_ram;
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15 |
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16 | architecture RTL of sync_ram is
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17 |
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18 | type ram_type is array (0 to 255) of std_logic_vector(datain'range);
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19 | signal ram : ram_type;
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20 |
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21 | begin
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22 |
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23 | process(clock) is
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24 | begin
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25 | if rising_edge(clock) then
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26 | if we = '1' then
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27 | ram(to_integer(unsigned(address))) <= datain;
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28 | else
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29 | dataout <= ram(to_integer(unsigned(read_address)));
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30 | end if;
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31 | end if;
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32 | end process;
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33 |
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34 | end architecture RTL;
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