UART mit RS232 Standard

library ieee; 

use ieee.std_logic_1164.all; 

use ieee.numeric_std.all; 

entity rs232_rx is

generic( 

  quarz_taktfrequenz : integer := 50000000;  

  baudrate           : integer := 19200

);  

port(

  clk     : in  std_logic;

  rxd     : in  std_logic;

  rx_en   : out std_logic;

  rx_data : out std_logic_vector (7 downto 0) 

);

end rs232_rx;

architecture behavioral of rs232_rx is

type rx_state_t is (idle, busy, ready);

signal rx_state : rx_state_t := idle;

signal rxd_sr   : std_logic_vector (3 downto 0) := "1111";         

signal rxsr     : std_logic_vector (7 downto 0) := "00000000";    

signal rxbitcnt : integer range 0 to 9 := 9;

signal rxcnt    : integer range 0 to (quarz_taktfrequenz/baudrate)-1;   

begin

process begin

wait until rising_edge(clk);   

  rxd_sr <= rxd_sr(rxd_sr'left-1 downto 0) & rxd;

  rx_en  <= '0';

  case rx_state is

  when idle => -- warten auf startbit

    if (rxd_sr(3 downto 2) = "10") then                 

      rxcnt    <= ((quarz_taktfrequenz/baudrate)-1)/2; 

      rxbitcnt <= 0;

      rx_state <= busy;

    end if;

  when busy =>

    if (rxbitcnt<9) then  

      if(rxcnt<(quarz_taktfrequenz/baudrate)-1) then 

        rxcnt    <= rxcnt+1;

      else

        rxcnt    <= 0; 

        rxbitcnt <= rxbitcnt+1;

        rxsr     <= rxd_sr(rxd_sr'left-1) & rxsr(rxsr'left downto 1); 

      end if;

    else

      rx_state <= ready;

    end if;

  when ready =>

    rx_data  <= rxsr;

    rx_state <= idle; 

    rx_en    <= '1';           

  end case;

end process;  

end behavioral;