Beim SRAM-Daten-übertragen wird immer als erstes Bit7 gesendet.

peter Gast #3949861
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Hallo, guten Tag.
Mit der VHDL kann ich über RS232 mit 19200 Baud Daten zum SRAM auf dem 
DE1 senden.
Die Datenkontrolle dafür sind die LED-rot. Das funktioniert.

Wenn ich den switch(2) betätige, werden die Byte aus dem SRAM gelesen 
und mit der
LED-grün angezeigt. Das funktioniert auch soweit. Nur wird beim 
Switch(2) betätigen
immer erst das Bit7 gesetzt von der LED-grün und dann die SRAM-daten so 
wie ich sie
vorher gesendet habe. Wie kann ich das umgehen das das Bit7 nicht 
leuchtet wenn ich den Switch(2)
betätige.

Danke.

Gruss

1
library IEEE;

2
use IEEE.STD_LOGIC_1164.ALL;

3
use IEEE.STD_LOGIC_ARITH.ALL;

4
use IEEE.STD_LOGIC_UNSIGNED.ALL;

5


6
entity sram_rx is

7
  port ( clk50    : in    std_logic;

8
         sw       : in    std_logic_vector ( 2 downto 0);

9
         ledg     : out   std_logic_vector ( 7 downto 0);

10
         ledr     : out   std_logic_vector ( 7 downto 0);

11
         

12
         raddr    : out   std_logic_vector (17 downto 0);

13
         rdata     : inout std_logic_vector (7 downto 0);

14
         

15
         ce        : out    std_logic;

16
         we        : out    std_logic;  

17
         oe        : out    std_logic;

18
         lb        : out    std_logic;

19
         ub        : out    std_logic;

20
         rxd      : in  std_logic

21
       );

22
end sram_rx;

23


24
architecture behavioral of sram_rx is

25


26
signal addr        : std_logic_vector ( 17 downto 0);  

27
signal data_sw    : std_logic_vector ( 7 downto 0);

28
signal state      : std_logic_vector ( 2 downto 0); 

29


30
signal rx_en   : std_logic;

31
signal rx_data : std_logic_vector (7 downto 0); 

32


33
signal cnt  : integer range 0 to 25000000; 

34


35
component rs232_rx port(

36
  clk50   : in  std_logic;

37
  rxd     : in  std_logic;

38
  rx_en   : out std_logic;

39
  rx_data : out std_logic_vector (7 downto 0) 

40
 );

41
end component;

42


43
begin

44


45
rx: rs232_rx

46
port map(

47
  clk50   => clk50,

48
  rxd     => rxd,

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  rx_en   => rx_en,

50
  rx_data => rx_data

51
);

52


53
process (clk50)

54
begin

55
  if rising_edge(clk50) then

56
    case state is

57
      --- idle state

58
      when "000"   =>  rdata   <= (others => 'Z');

59
      

60
      --- write state

61
      when "001"  =>   raddr   <= addr; 

62
                      rdata   <= data_sw; 

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                      ce       <= '0'; 

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                      oe       <= '1'; 

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                      we       <= '1'; 

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                      lb      <= '0';

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                      ub      <= '0';

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                      state   <= "010";

69
                      

70
      when "010"  =>   ce       <= '1'; 

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                      we       <= '0'; 

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                      state   <= "011";

73
                      

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      when "011"  =>   ce       <= '0'; 

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                      rdata   <= data_sw; 

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                      state   <= "000";

77


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      --- read state

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      when "100"  =>   raddr   <= addr; 

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                      rdata   <= (others => 'Z'); 

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                      ce       <= '0'; 

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                      oe       <= '0'; 

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                      we       <= '1';                           

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                      lb      <= '0';

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                      ub      <= '0';

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                      state   <= "101";

87
                      

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      when "101"  =>   ce       <= '1'; 

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                      we       <= '1';

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                      state   <= "110";

91
                      

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      when "110"  =>   ce       <= '0'; 

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                      oe       <= '1';

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                      ledg    <= rdata;

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                      state   <= "000";

96
                      

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      when others => state     <= "000";

98
    end case;

99
    

100
    if rx_en='1' then 

101
      addr    <= addr+1;

102
      data_sw <= rx_data; 

103
      ledr    <= rx_data;

104
      state   <= "001";

105
    end if;  

106
     

107
    if sw(0) = '1' then

108
      rdata   <= (others => 'Z');

109
      raddr   <= (others => '0');

110
      we      <= '1';

111
      ce      <= '1';

112
      oe      <= '1'; 

113
    end if;

114
    

115
    if sw(1) = '1' then

116
      addr    <= (others => '0');

117
      data_sw <= (others => '0');

118
      ledr    <= (others => '0');

119
      ledg    <= (others => '0');

120
    end if;

121
    

122
    if sw(2) = '1' and addr < 255 then

123
      if (cnt<2000000)  then 

124
        cnt  <= cnt+1;

125
      else

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        cnt   <= 0; 

127
        state <= "100";

128
        addr  <=addr+1;

129
      end if;  

130
    end if; 

131
       

132
  end if;

133
end process;

134


135
end behavioral;

136


137
------------------------------------------------------

138
library ieee; 

139
use ieee.std_logic_1164.all; 

140
use ieee.numeric_std.all; 

141


142
entity rs232_rx is

143
generic( 

144
  quarz_taktfrequenz : integer := 50000000;  

145
  baudrate           : integer := 19200

146
);  

147
    

148
port(

149
  clk50    : in  std_logic;

150
  rxd     : in  std_logic;

151
  rx_en   : out std_logic;

152
  rx_data : out std_logic_vector (7 downto 0) 

153
);

154
end rs232_rx;

155


156
architecture behavioral of rs232_rx is

157


158
type rx_state_t is (idle, busy, ready);

159
signal rx_state : rx_state_t := idle;

160


161
signal rxd_sr   : std_logic_vector (3 downto 0) := "1111";         

162
signal rxsr     : std_logic_vector (7 downto 0) := "00000000";    

163
signal rxbitcnt : integer range 0 to 9 := 9;

164
signal rxcnt    : integer range 0 to (quarz_taktfrequenz/baudrate)-1;   

165


166
begin

167


168
process begin

169
wait until rising_edge(clk50);   

170
  rxd_sr <= rxd_sr(rxd_sr'left-1 downto 0) & rxd;

171
  rx_en  <= '0';

172


173
  case rx_state is

174
  when idle => -- warten auf startbit

175
    if (rxd_sr(3 downto 2) = "10") then                 

176
      rxcnt    <= ((quarz_taktfrequenz/baudrate)-1)/2; 

177
      rxbitcnt <= 0;

178
      rx_state <= busy;

179
    end if;

180
    

181
  when busy =>

182
    if (rxbitcnt<9) then  

183
      if(rxcnt<(quarz_taktfrequenz/baudrate)-1) then 

184
        rxcnt    <= rxcnt+1;

185
      else

186
        rxcnt    <= 0; 

187
        rxbitcnt <= rxbitcnt+1;

188
        rxsr     <= rxd_sr(rxd_sr'left-1) & rxsr(rxsr'left downto 1); 

189
      end if;

190
    else

191
      rx_state <= ready;

192
    end if;

193
    

194
  when ready =>

195
    rx_data  <= rxsr;

196
    rx_state <= idle; 

197
    rx_en    <= '1';           

198
  end case;

199
end process;  

200


201
end behavioral;
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peter Gast #3950013
Lesenswert?
• ▲
▼ 
Habe es mal auf Datenleitung 0-15 erweitert.

Gruss

1
library IEEE;

2
use IEEE.STD_LOGIC_1164.ALL;

3
use IEEE.NUMERIC_STD.ALL;

4
use IEEE.STD_LOGIC_UNSIGNED.ALL;

5


6
entity sram_rx is

7
  port ( clk50    : in    std_logic;

8
         sw       : in    std_logic_vector ( 2 downto 0);

9
         ledg     : out   std_logic_vector ( 7 downto 0);

10
         ledr     : out   std_logic_vector ( 7 downto 0);

11
         

12
         raddr    : out   std_logic_vector (17 downto 0);

13
         rdata     : inout std_logic_vector (15 downto 0);

14
         

15
         ce        : out    std_logic;

16
         we        : out    std_logic;  

17
         oe        : out    std_logic;

18
         lb        : out    std_logic;

19
         ub        : out    std_logic;

20
         rxd      : in  std_logic

21
       );

22
end sram_rx;

23


24
architecture behavioral of sram_rx is

25


26
signal addr        : std_logic_vector ( 17 downto 0);  

27
signal data_sw    : std_logic_vector ( 7 downto 0);

28
signal data_in    : std_logic_vector ( 7 downto 0);

29
signal state      : std_logic_vector ( 2 downto 0); 

30


31
signal rx_en   : std_logic;

32
signal rx_data : std_logic_vector (7 downto 0); 

33


34
signal cnt  : integer range 0 to 25000000; 

35


36
component rs232_rx port(

37
  clk50   : in  std_logic;

38
  rxd     : in  std_logic;

39
  rx_en   : out std_logic;

40
  rx_data : out std_logic_vector (7 downto 0) 

41
 );

42
end component;

43


44
begin

45


46
rx: rs232_rx

47
port map(

48
  clk50   => clk50,

49
  rxd     => rxd,

50
  rx_en   => rx_en,

51
  rx_data => rx_data

52
);

53


54
process (clk50)

55
begin

56
  if rising_edge(clk50) then

57
    case state is

58
      --- idle state

59
      when "000"   =>  rdata   <= (others => 'Z');

60
      

61
      --- write state

62
      when "001"  =>   raddr   <= addr; 

63
                      rdata   <= "00000000" & data_sw; 

64
                      ce       <= '0'; 

65
                      oe       <= '1'; 

66
                      we       <= '1'; 

67
                      lb      <= '0';

68
                      ub      <= '0';

69
                      state   <= "010";

70
                      

71
      when "010"  =>   ce       <= '1'; 

72
                      we       <= '0'; 

73
                      state   <= "011";

74
                      

75
      when "011"  =>   ce       <= '0'; 

76
                      rdata   <= "00000000" & data_sw; 

77
                      state   <= "000";

78


79
      --- read state

80
      when "100"  =>   raddr   <= addr; 

81
                      rdata   <= (others => 'Z'); 

82
                      ce       <= '0'; 

83
                      oe       <= '0'; 

84
                      we       <= '1';                           

85
                      lb      <= '0';

86
                      ub      <= '0';

87
                      state   <= "101";

88
                      

89
      when "101"  =>   ce       <= '1'; 

90
                      we       <= '1';

91
                      state   <= "110";

92
                      

93
      when "110"  =>   ce       <= '0'; 

94
                      oe       <= '1';

95
                      data_in <= rdata(7 downto 0);

96
                      state   <= "000";

97
                      

98
      when others => state     <= "000";

99
    end case;

100
    

101
    if rx_en='1' then 

102
      addr    <= addr+1;

103
      data_sw <= rx_data; 

104
      state   <= "001";

105
    end if;  

106
     

107
    if sw(0) = '1' then

108
      rdata   <= (others => 'Z');

109
      raddr   <= (others => '0');

110
      we      <= '1';

111
      ce      <= '1';

112
      oe      <= '1'; 

113
    end if;

114
    

115
    if sw(1) = '1' then

116
      addr    <= (others => '0');

117
      data_sw <= (others => '0');

118
    end if;

119
    

120
    if sw(2) = '1' and addr < 255 then

121
      if (cnt < 2000000)  then 

122
        cnt  <= cnt+1;

123
      else

124
        cnt   <= 0; 

125
        state <= "100";

126
        addr  <=addr+1;

127
      end if;  

128
    end if; 

129
  end if;

130
end process;

131


132
ledg <= data_in;

133
ledr <= rx_data;   

134
end behavioral;
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