MSP430 SMCLK = XT1CLK != 32 kHz?

#include <msp430.h> 

int main(void)

{

    WDTCTL = WDTPW | WDTHOLD;  // Stop watchdog timer

    // XT1 Setup

    PJSEL0 |= BIT4 + BIT5;

    // Configure P3.4 = SMCLK

    P3DIR |= BIT4;

    P3SEL0 |= BIT4;

    P3SEL1 |= BIT4;

    // Configure MSCLK = XT1CLK

    CSCTL0_H = 0xA5;

    CSCTL2 = SELS_0;          // set ACLK = XT1CLK

    CSCTL3 = DIVS_0;          // set ACLK Divider = 1

    CSCTL4 &= ~SMCLKOFF;

    CSCTL4 &= ~XT1OFF;        // Start XT1

    CSCTL4 &= ~XTS;

    CSCTL4 |= XT1DRIVE_0;

    CSCTL0_H = 0x01;          // Lock Register

    return 0;

}