XNOR mit 4:1 MUX

entity mux_gate is

  port(

    D0 ,D1 ,D2 ,D3 ,S0 ,S1 : in STD_LOGIC;

    Y : out STD_LOGIC

  );

end mux_gate;

architecture mux_behavior of mux_gate is

begin

  P1:process(D0,D1,D2,D3,S0,S1)

  begin

      if (S0='0' and S1='0') then Y<=D0; elsif

      (S0='0' and S1='1')    then Y<=D1; elsif

      (S0='1' and S1='0')    then Y<=D2; else

       Y<=D3;

       end if;

  end process P1;

end mux_behavior;

.....

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entity eq_gate is

  port(

  in0,in1 : in STD_LOGIC;

  out0 : out STD_LOGIC

  );

end eq_gate;

architecture eq_dataflow of eq_gate is

begin

out0 <= (in0 and in1) or (not in0 and not in1);

end eq_dataflow;

architecture eq_structure of eq_gate is

????

end eq_structure;