verilog syntax verständnis

  lpm_ram_dp info_fifo

  (

//...

    .data      (len_cnt & {4{~initialize_memories}}),

 );

input [3:0] data;//(4 bit)

//...

reg     [3:0] len_cnt; //(4 bit)

reg           initialize_memories;//(1 bit)

  PORT MAP

  (

    data      => len_cnt and (not initialize_memories), -- so nicht